72 lines
955 B
Systemverilog
72 lines
955 B
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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module uart_tb();
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logic clk;
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logic rst;
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logic [7:0] tx_data, rx_data;
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logic tx_start, rx_ready;
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logic tx_busy, rx_busy;
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logic txd;
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uart_tx #(
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.DATA_WIDTH(8),
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.CLK_FREQ_HZ(100_000_000),
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.BAUDRATE(115200))
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tx (
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.clk(clk),
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.rst(rst),
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.data(tx_data),
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.start(tx_start),
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.busy(tx_busy),
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.txd(txd));
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uart_rx #(
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.DATA_WIDTH(8),
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.CLK_FREQ_HZ(100_000_000),
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.BAUDRATE(115200))
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rx (
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.clk(clk),
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.rst(rst),
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.rxd(txd),
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.data(rx_data),
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.ready(rx_ready),
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.busy(rx_busy));
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always begin
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#5;
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clk = !clk;
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end
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initial begin
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$dumpfile("uart.vcd");
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$dumpvars(0, uart_tb);
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clk = 0;
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rst = 1;
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tx_data = 'h0F;
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tx_start = 0;
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#10;
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rst = 0;
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#10;
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tx_start = 1;
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#10;
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tx_start = 0;
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#150000;
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// send another byte!
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tx_data = 'hBE;
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tx_start = 1;
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#10;
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tx_start = 0;
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#150000;
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$finish();
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end
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endmodule
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`default_nettype wire
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