125 lines
3.5 KiB
Verilog
125 lines
3.5 KiB
Verilog
`default_nettype none
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`timescale 1ns/1ps
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module trigger_block(
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input wire clk,
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// probes
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input wire larry,
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input wire curly,
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input wire moe,
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input wire [3:0] shemp,
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// trigger
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output reg trig,
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// input port
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input wire [15:0] addr_i,
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input wire [15:0] wdata_i,
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input wire [15:0] rdata_i,
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input wire rw_i,
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input wire valid_i,
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// output port
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output reg [15:0] addr_o,
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output reg [15:0] wdata_o,
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output reg [15:0] rdata_o,
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output reg rw_o,
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output reg valid_o);
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parameter BASE_ADDR = 0;
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// trigger configuration registers
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// - each probe gets an operation and a compare register
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// - at the end we OR them all together. along with any custom probes the user specs
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reg [3:0] larry_trigger_op = 0;
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reg larry_trigger_arg = 0;
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reg larry_trig;
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trigger #(.INPUT_WIDTH(1)) larry_trigger(
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.clk(clk),
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.probe(larry),
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.op(larry_trigger_op),
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.arg(larry_trigger_arg),
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.trig(larry_trig));
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reg [3:0] curly_trigger_op = 0;
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reg curly_trigger_arg = 0;
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reg curly_trig;
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trigger #(.INPUT_WIDTH(1)) curly_trigger(
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.clk(clk),
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.probe(curly),
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.op(curly_trigger_op),
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.arg(curly_trigger_arg),
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.trig(curly_trig));
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reg [3:0] moe_trigger_op = 0;
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reg moe_trigger_arg = 0;
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reg moe_trig;
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trigger #(.INPUT_WIDTH(1)) moe_trigger(
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.clk(clk),
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.probe(moe),
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.op(moe_trigger_op),
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.arg(moe_trigger_arg),
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.trig(moe_trig));
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reg [3:0] shemp_trigger_op = 0;
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reg [3:0] shemp_trigger_arg = 0;
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reg shemp_trig;
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trigger #(.INPUT_WIDTH(4)) shemp_trigger(
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.clk(clk),
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.probe(shemp),
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.op(shemp_trigger_op),
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.arg(shemp_trigger_arg),
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.trig(shemp_trig));
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assign trig = larry_trig || curly_trig || moe_trig || shemp_trig;
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// perform register operations
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always @(posedge clk) begin
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addr_o <= addr_i;
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wdata_o <= wdata_i;
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rdata_o <= rdata_i;
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rw_o <= rw_i;
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valid_o <= valid_i;
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rdata_o <= rdata_i;
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if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + 7) ) begin
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// reads
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if(valid_i && !rw_i) begin
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case (addr_i)
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BASE_ADDR + 0: rdata_o <= larry_trigger_op;
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BASE_ADDR + 1: rdata_o <= larry_trigger_arg;
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BASE_ADDR + 2: rdata_o <= curly_trigger_op;
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BASE_ADDR + 3: rdata_o <= curly_trigger_arg;
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BASE_ADDR + 4: rdata_o <= moe_trigger_op;
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BASE_ADDR + 5: rdata_o <= moe_trigger_arg;
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BASE_ADDR + 6: rdata_o <= shemp_trigger_op;
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BASE_ADDR + 7: rdata_o <= shemp_trigger_arg;
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endcase
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end
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// writes
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else if(valid_i && rw_i) begin
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case (addr_i)
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BASE_ADDR + 0: larry_trigger_op <= wdata_i;
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BASE_ADDR + 1: larry_trigger_arg <= wdata_i;
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BASE_ADDR + 2: curly_trigger_op <= wdata_i;
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BASE_ADDR + 3: curly_trigger_arg <= wdata_i;
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BASE_ADDR + 4: moe_trigger_op <= wdata_i;
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BASE_ADDR + 5: moe_trigger_arg <= wdata_i;
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BASE_ADDR + 6: shemp_trigger_op <= wdata_i;
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BASE_ADDR + 7: shemp_trigger_arg <= wdata_i;
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endcase
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end
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end
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end
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endmodule
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`default_nettype wire |