74 lines
2.4 KiB
Python
74 lines
2.4 KiB
Python
from amaranth import *
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from amaranth.lib import io
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from manta import *
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class UARTMemoryCoreExample(Elaboratable):
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def __init__(self, platform, port):
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self.platform = platform
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# Create Manta instance
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self.manta = Manta()
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# Configure it to communicate over Ethernet
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self.manta.interface = UARTInterface(
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port=port,
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baudrate=2000000,
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clock_freq=platform.default_clk_frequency,
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)
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# Add IOCore to Manta instance
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self.manta.cores.mem = MemoryCore(mode="host_to_fpga", width=16, depth=512)
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def elaborate(self, platform):
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m = Module()
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# Add Manta as a submodule
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m.submodules.manta = self.manta
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# Wire each LED to the data output of the memory core
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for i in range(16):
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led = io.Buffer("o", platform.request("led", i, dir="-"))
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m.d.comb += led.o.eq(self.manta.cores.mem.user_data_out[i])
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m.submodules += led
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# Wire each switch to the address input of the memory core
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for i in range(9):
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sw = io.Buffer("i", platform.request("switch", i, dir="-"))
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m.d.comb += self.manta.cores.mem.user_addr[i].eq(sw.i)
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m.submodules += sw
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# Wire UART pins to the Manta instance
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uart_pins = platform.request("uart", dir={"tx": "-", "rx": "-"})
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m.submodules.uart_rx = uart_rx = io.Buffer("i", uart_pins.rx)
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m.submodules.uart_tx = uart_tx = io.Buffer("o", uart_pins.tx)
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m.d.comb += self.manta.interface.rx.eq(uart_rx.i)
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m.d.comb += uart_tx.o.eq(self.manta.interface.tx)
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return m
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def test(self):
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# Build and program the FPGA
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self.platform.build(self, do_program=True)
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# Iterate through all the LEDs, blinking them off and on
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i = 0
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for i in range(512):
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self.manta.cores.mem.write(i, i)
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# Amaranth has a built-in build system, and well as a set of platform
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# definitions for a huge number of FPGA boards. The class defined above is
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# very generic, as it specifies a design independent of any particular FGPA
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# board. This means that by changing which platform you pass UARTIOCoreExample
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# below, you can port this example to any FPGA board!
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if __name__ == "__main__":
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from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
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UARTMemoryCoreExample(
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platform=Nexys4DDRPlatform(),
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port="auto",
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).test()
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