312 lines
8.3 KiB
Systemverilog
312 lines
8.3 KiB
Systemverilog
`default_nettype none
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`define CP 10
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`define HCP 5
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task read_reg (
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input [15:0] addr,
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output [15:0] data,
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input string desc
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);
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logic_analyzer_tb.tb_la_addr = addr;
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logic_analyzer_tb.tb_la_rw = 0;
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logic_analyzer_tb.tb_la_valid = 1;
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#`CP
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logic_analyzer_tb.tb_la_valid = 0;
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while (!logic_analyzer_tb.la_tb_valid) #`CP;
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data = logic_analyzer_tb.la_tb_rdata;
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$display(" -> read 0x%h from addr 0x%h (%s)", data, addr, desc);
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endtask
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task write_reg(
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input [15:0] addr,
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input [15:0] data,
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input string desc
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);
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logic_analyzer_tb.tb_la_addr = addr;
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logic_analyzer_tb.tb_la_wdata = data;
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logic_analyzer_tb.tb_la_rw = 1;
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logic_analyzer_tb.tb_la_valid = 1;
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#`CP
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logic_analyzer_tb.tb_la_valid = 0;
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while (!logic_analyzer_tb.la_tb_valid) #`CP;
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$display(" -> wrote 0x%h to addr 0x%h (%s)", data, addr, desc);
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endtask
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task write_and_verify(
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input [15:0] addr,
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input [15:0] write_data,
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input string desc
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);
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reg [15:0] read_data;
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write_reg(addr, write_data, desc);
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read_reg(addr, read_data, desc);
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assert(read_data == write_data) else $error("data read does not match data written!");
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endtask
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task read_all_reg();
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string desc;
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for(int i = 0; i < (logic_analyzer_tb.la.sample_mem.BASE_ADDR + logic_analyzer_tb.la.SAMPLE_DEPTH); i++) begin
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if(i == logic_analyzer_tb.la.fsm.BASE_ADDR) desc = "FSM";
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if(i == logic_analyzer_tb.la.trig_blk.BASE_ADDR) desc = "TRIG BLK";
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if(i == logic_analyzer_tb.la.sample_mem.BASE_ADDR) desc = "SAMPLE MEM";
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read_reg(i, logic_analyzer_tb.read_value, desc);
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end
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endtask
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module logic_analyzer_tb;
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// boilerplate
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logic clk;
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integer test_num;
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// signal generator
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logic larry;
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logic curly;
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logic moe;
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logic [3:0] shemp;
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// tb -> la bus
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logic [15:0] tb_la_addr;
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logic [15:0] tb_la_wdata;
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logic [15:0] tb_la_rdata;
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logic tb_la_rw;
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logic tb_la_valid;
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// la -> tb bus
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logic [15:0] la_tb_addr;
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logic [15:0] la_tb_wdata;
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logic [15:0] la_tb_rdata;
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logic la_tb_rw;
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logic la_tb_valid;
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logic_analyzer #(.BASE_ADDR(0), .SAMPLE_DEPTH(128)) la(
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.clk(clk),
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// probes
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.larry(larry),
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.curly(curly),
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.moe(moe),
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.shemp(shemp),
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// input port
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.addr_i(tb_la_addr),
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.wdata_i(tb_la_wdata),
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.rdata_i(tb_la_rdata),
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.rw_i(tb_la_rw),
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.valid_i(tb_la_valid),
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// output port
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.addr_o(la_tb_addr),
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.wdata_o(la_tb_wdata),
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.rdata_o(la_tb_rdata),
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.rw_o(la_tb_rw),
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.valid_o(la_tb_valid));
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always begin
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#`HCP
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clk = !clk;
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end
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reg [15:0] read_value;
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initial begin
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$dumpfile("logic_analyzer_tb.vcd");
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$dumpvars(0, logic_analyzer_tb);
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// setup and reset
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clk = 0;
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test_num = 0;
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tb_la_addr = 0;
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tb_la_rdata = 0;
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tb_la_wdata = 0;
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tb_la_rw = 0;
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tb_la_valid = 0;
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larry = 0;
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curly = 0;
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moe = 0;
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shemp = 0;
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#`HCP
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#(10*`CP);
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/* ==== Test 1 Begin ==== */
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$display("\n=== test 1: read/write to FSM registers, verify ===");
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test_num = 1;
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// state register
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write_and_verify(0, la.fsm.IDLE, "state reg");
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write_and_verify(0, la.fsm.FILLED, "state reg");
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write_and_verify(0, la.fsm.IDLE, "state reg");
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// trigger_loc register
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write_and_verify(1, 0, "trigger_loc reg");
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write_and_verify(1, 'h69, "trigger_loc reg");
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write_and_verify(1, 'h0612, "trigger_loc reg");
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// since we just moved the trigger location, the core has started moving into position
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// if it's functioning correctly. this means we need to reset the position and state
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// before testing the present_loc register.
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// write_and_verify(1, 0, "trigger_loc reg");
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// write_and_verify(0, 0, "state reg");
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// // present_loc register
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// write_and_verify(2, 0, "present_loc reg");
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// write_and_verify(2, 0, "present_loc reg");
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#(10*`CP);
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/* ==== Test 1 End ==== */
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/* ==== Test 2 Begin ==== */
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$display("\n=== test 2: read/write to trigger block registers, verify ===");
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test_num = 2;
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// larry
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write_and_verify(3, 0, "larry_op");
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write_and_verify(3, 2, "larry_op");
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write_and_verify(3, 0, "larry_op");
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write_and_verify(4, 0, "larry_arg");
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write_and_verify(4, 1, "larry_arg");
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write_and_verify(4, 0, "larry_arg");
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// curly
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write_and_verify(5, 0, "curly_op");
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write_and_verify(5, 3, "curly_op");
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write_and_verify(5, 0, "curly_op");
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write_and_verify(6, 0, "curly_arg");
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write_and_verify(6, 1, "curly_arg");
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write_and_verify(6, 0, "curly_arg");
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// moe
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write_and_verify(7, 0, "moe_op");
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write_and_verify(7, 5, "moe_op");
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write_and_verify(7, 0, "moe_op");
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write_and_verify(8, 0, "moe_arg");
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write_and_verify(8, 1, "moe_arg");
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write_and_verify(8, 0, "moe_arg");
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// shemp
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write_and_verify(9, 0, "shemp_op");
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write_and_verify(9, 7, "shemp_op");
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write_and_verify(9, 0, "shemp_op");
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write_and_verify(10, 0, "shemp_arg");
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write_and_verify(10, 7, "shemp_arg");
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write_and_verify(10, 0, "shemp_arg");
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#(10*`CP);
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/* ==== Test 2 End ==== */
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/* ==== Test 3 Begin ==== */
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$display("\n=== test 3: verify FSM doesn't move out of IDLE when not running ===");
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test_num = 3;
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write_and_verify(3, 8, "larry_op"); // set operation to eq
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write_and_verify(4, 1, "larry_arg"); // set argument to 1
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// set larry = 1, verify core doesn't trigger
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$display(" -> set larry = 1");
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larry = 1;
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$display(" -> la core is in state 0x%h", la.fsm.state);
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assert(la.fsm.state == la.fsm.IDLE) else $error("core moved outside of IDLE state when not running!");
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$display(" -> wait a clock cycle");
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#`CP
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$display(" -> la core is in state 0x%h", la.fsm.state);
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assert(la.fsm.state == la.fsm.IDLE) else $error("core moved outside of IDLE state when not running!");
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$display(" -> set larry = 0");
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larry = 0;
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#(10*`CP);
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/* ==== Test 3 End ==== */
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/* ==== Test 4 Begin ==== */
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$display("\n=== test 4: verify FSM does move out of IDLE when running ===");
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test_num = 4;
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$display(" -> moving core to START_CAPTURE");
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write_reg(0, 1, "state");
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#`CP
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$display(" -> set larry = 1");
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larry = 1;
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// read
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$display(" -> la core is in state 0x%h", la.fsm.state);
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$display(" -> wait a clock cycle");
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#`CP
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$display(" -> la core is in state 0x%h", la.fsm.state);
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// run until the FILLED state is reached
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$display(" -> wait until FILLED state is reached");
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while (la.fsm.state != la.fsm.FILLED) begin
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{larry, curly, moe, shemp} = {larry, curly, moe, shemp} + 1;
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#`CP;
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end
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$display(" -> read from sample memory:");
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read_all_reg();
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#(200*`CP);
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/* ==== Test 4 End ==== */
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/* ==== Test 5 Begin ==== */
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$display("\n=== test 5: change trigger to fire on shemp > 3, and verify ===");
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test_num = 5;
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write_and_verify(9, 6, "shemp_op"); // set operation to GT
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write_and_verify(10, 3, "shemp_arg"); // set argument to 3
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assert( (la.fsm.state == la.fsm.IDLE) || (la.fsm.state == la.fsm.FILLED) )
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else $error("core is running when it shouldn't be!");
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larry = 0;
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curly = 0;
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moe = 0;
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shemp = 0;
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write_reg(0, la.fsm.START_CAPTURE, "state");
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shemp = 4;
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$display(" -> set shemp = 4");
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// run until the FILLED state is reached
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$display(" -> wait until FILLED state is reached");
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while (la.fsm.state != la.fsm.FILLED) begin
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{larry, curly, moe, shemp} = {larry, curly, moe, shemp} + 2;
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#`CP;
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end
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$display(" -> read from sample memory:");
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read_all_reg();
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#(10*`CP);
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/* ==== Test 5 End ==== */
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$finish();
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end
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endmodule
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`default_nettype wire |