126 lines
2.9 KiB
Verilog
126 lines
2.9 KiB
Verilog
`default_nettype none
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`timescale 1ns/1ps
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module logic_analyzer(
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input wire clk,
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// probes
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input wire larry,
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input wire curly,
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input wire moe,
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input wire [3:0] shemp,
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// input port
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input wire [15:0] addr_i,
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input wire [15:0] wdata_i,
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input wire [15:0] rdata_i,
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input wire rw_i,
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input wire valid_i,
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// output port
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output reg [15:0] addr_o,
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output reg [15:0] wdata_o,
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output reg [15:0] rdata_o,
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output reg rw_o,
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output reg valid_o
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);
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parameter BASE_ADDR = 0;
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parameter SAMPLE_DEPTH = 0;
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// fsm
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la_fsm #(.BASE_ADDR(BASE_ADDR), .SAMPLE_DEPTH(SAMPLE_DEPTH)) fsm (
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.clk(clk),
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.trig(trig),
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.fifo_size(fifo_size),
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.fifo_acquire(fifo_acquire),
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.fifo_pop(fifo_pop),
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.fifo_clear(fifo_clear),
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.addr_i(addr_i),
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.wdata_i(wdata_i),
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.rdata_i(rdata_i),
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.rw_i(rw_i),
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.valid_i(valid_i),
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.addr_o(fsm_trig_blk_addr),
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.wdata_o(fsm_trig_blk_wdata),
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.rdata_o(fsm_trig_blk_rdata),
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.rw_o(fsm_trig_blk_rw),
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.valid_o(fsm_trig_blk_valid));
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reg [15:0] fsm_trig_blk_addr;
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reg [15:0] fsm_trig_blk_wdata;
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reg [15:0] fsm_trig_blk_rdata;
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reg fsm_trig_blk_rw;
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reg fsm_trig_blk_valid;
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reg trig;
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reg [$clog2(SAMPLE_DEPTH):0] fifo_size;
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reg fifo_acquire;
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reg fifo_pop;
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reg fifo_clear;
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// trigger block
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trigger_block #(.BASE_ADDR(BASE_ADDR + 3)) trig_blk(
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.clk(clk),
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.larry(larry),
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.curly(curly),
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.moe(moe),
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.shemp(shemp),
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.trig(trig),
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.addr_i(fsm_trig_blk_addr),
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.wdata_i(fsm_trig_blk_wdata),
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.rdata_i(fsm_trig_blk_rdata),
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.rw_i(fsm_trig_blk_rw),
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.valid_i(fsm_trig_blk_valid),
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.addr_o(trig_blk_sample_mem_addr),
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.wdata_o(trig_blk_sample_mem_wdata),
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.rdata_o(trig_blk_sample_mem_rdata),
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.rw_o(trig_blk_sample_mem_rw),
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.valid_o(trig_blk_sample_mem_valid));
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reg [15:0] trig_blk_sample_mem_addr;
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reg [15:0] trig_blk_sample_mem_wdata;
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reg [15:0] trig_blk_sample_mem_rdata;
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reg trig_blk_sample_mem_rw;
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reg trig_blk_sample_mem_valid;
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// sample memory
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sample_mem #(.BASE_ADDR(BASE_ADDR + 11), .SAMPLE_DEPTH(SAMPLE_DEPTH)) sample_mem(
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.clk(clk),
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// fifo
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.acquire(fifo_acquire),
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.pop(fifo_pop),
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.size(fifo_size),
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.clear(fifo_clear),
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// probes
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.larry(larry),
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.curly(curly),
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.moe(moe),
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.shemp(shemp),
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// input port
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.addr_i(trig_blk_sample_mem_addr),
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.wdata_i(trig_blk_sample_mem_wdata),
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.rdata_i(trig_blk_sample_mem_rdata),
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.rw_i(trig_blk_sample_mem_rw),
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.valid_i(trig_blk_sample_mem_valid),
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// output port
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.addr_o(addr_o),
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.wdata_o(wdata_o),
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.rdata_o(rdata_o),
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.rw_o(rw_o),
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.valid_o(valid_o));
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endmodule
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`default_nettype wire |