Fischer Moseley ab8582a570 move building examples into makefile, add working logic analyzer test		2023-04-03 23:47:36 -04:00
..
src	move building examples into makefile, add working logic analyzer test	2023-04-03 23:47:36 -04:00
xdc	rename lut mem to lut ram, add to manta generator	2023-03-14 16:24:56 -04:00
lab-bc.py	rename lut mem to lut ram, add to manta generator	2023-03-14 16:24:56 -04:00
manta.yaml	add ability to autodetect serial port	2023-03-23 20:46:49 -04:00
read_write_test.py	add lut ram operations to Python API	2023-03-23 19:38:19 -04:00