32 lines
511 B
Systemverilog
32 lines
511 B
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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`include "manta.v"
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module top_level (
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input wire clk,
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output logic LED0,
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output logic LED1,
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output logic LED2,
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output logic LED3,
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output logic LED4,
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input wire rs232_rx_ttl,
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output logic rs232_tx_ttl
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);
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manta manta_inst (
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.clk(clk),
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.rx(rs232_rx_ttl),
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.tx(rs232_tx_ttl),
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.LED0(LED0),
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.LED1(LED1),
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.LED2(LED2),
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.LED3(LED3),
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.LED4(LED4));
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endmodule
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`default_nettype wire |