28 lines
692 B
Systemverilog
28 lines
692 B
Systemverilog
`timescale 1ns / 1ps
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// Audio PWM module.
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module audio_PWM(
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input clk, // 100MHz clock.
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input reset, // Reset assertion.
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input [7:0] music_data, // 8-bit music sample
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output reg PWM_out // PWM output. Connect this to ampPWM.
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);
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reg [7:0] pwm_counter = 8'd0; // counts up to 255 clock cycles per pwm period
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always @(posedge clk) begin
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if(reset) begin
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pwm_counter <= 0;
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PWM_out <= 0;
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end
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else begin
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pwm_counter <= pwm_counter + 1;
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if(pwm_counter >= music_data) PWM_out <= 0;
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else PWM_out <= 1;
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end
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end
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endmodule
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