163 lines
5.2 KiB
Python
163 lines
5.2 KiB
Python
import yaml
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from amaranth import *
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from manta.ethernet import EthernetInterface
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from manta.io_core import IOCore
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from manta.logic_analyzer import LogicAnalyzerCore
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from manta.memory_core import MemoryCore
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from manta.uart import UARTInterface
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from manta.utils import *
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class Manta(Elaboratable):
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def __init__(self):
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self._interface = None
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self.cores = CoreContainer(self)
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# This treats the `interface` attribute as a property, which allows the
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# setter to update the interfaces of all the cores in self.cores whenever
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# the user assigns to Manta's `interface` object.
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@property
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def interface(self):
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return self._interface
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@interface.setter
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def interface(self, value):
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self._interface = value
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for core in self.cores._cores.values():
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core.interface = value
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@classmethod
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def from_config(cls, config_path):
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# Load config from YAML
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extension = config_path.split(".")[-1]
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if extension not in ["yaml", "yml"]:
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raise ValueError(f"Configuration file {config_path} has unrecognized file type.")
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with open(config_path, "r") as f:
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config = yaml.safe_load(f)
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# Validate config
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if "cores" not in config:
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raise ValueError("No cores specified in configuration file.")
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if not len(config["cores"]) > 0:
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raise ValueError("Must specify at least one core.")
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for name, attrs in config["cores"].items():
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# Make sure core type is specified
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if "type" not in attrs:
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raise ValueError(f"No type specified for core {name}.")
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if attrs["type"] not in ["logic_analyzer", "io", "memory"]:
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raise ValueError(f"Unrecognized core type specified for {name}.")
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# Make Manta object, and configure it
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manta = Manta()
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# Add interface
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if "uart" in config:
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manta.interface = UARTInterface.from_config(config["uart"])
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elif "ethernet" in config:
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manta.interface = EthernetInterface.from_config(config["ethernet"])
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# Add cores
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for name, attrs in config["cores"].items():
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if attrs["type"] == "io":
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core = IOCore.from_config(attrs)
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elif attrs["type"] == "logic_analyzer":
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core = LogicAnalyzerCore.from_config(attrs)
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elif attrs["type"] == "memory":
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core = MemoryCore.from_config(attrs)
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setattr(manta.cores, name, core)
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return manta
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def elaborate(self, platform):
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m = Module()
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# Add interface as submodule
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m.submodules.interface = self.interface
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# Add all cores as submodules
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for name, instance in self.cores._cores.items():
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m.submodules[name] = instance
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# Connect first/last cores to interface output/input respectively
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core_instances = list(self.cores._cores.values())
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first_core = core_instances[0]
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last_core = core_instances[-1]
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m.d.comb += first_core.bus_i.eq(self.interface.bus_o)
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m.d.comb += self.interface.bus_i.eq(last_core.bus_o)
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# Connect output of ith core to input of (i+1)th core
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for i in range(len(core_instances) - 1):
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ith_core = core_instances[i]
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i_plus_oneth_core = core_instances[i + 1]
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m.d.comb += i_plus_oneth_core.bus_i.eq(ith_core.bus_o)
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return m
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def get_top_level_ports(self):
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"""
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Return the Amaranth signals that should be included as ports in the
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top-level Manta module.
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"""
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ports = self.interface.get_top_level_ports()
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for name, instance in self.cores._cores.items():
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ports += instance.top_level_ports
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return ports
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def generate_verilog(self, path, strip_internal_attrs=False):
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from amaranth.back import verilog
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output = verilog.convert(
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self,
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name="manta",
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ports=self.get_top_level_ports(),
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strip_internal_attrs=strip_internal_attrs,
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)
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# Below is a hack!
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# The Ethernet core is a Verilog snippet generated by LiteEth,
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# which gets appended to the Amaranth output such that everything
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# still lives within one file.
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# In the future this shouldn't be required once Amaranth SOC
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# launches, but until then, this is likely the simplest approach.
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if isinstance(self.interface, EthernetInterface):
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output += self.interface.generate_liteeth_core()
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with open(path, "w") as f:
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f.write(output)
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def export_config(self, path):
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"Export a YAML file containing all the configuration of the core"
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config = {}
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if self.cores._cores:
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config["cores"] = {}
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for name, instance in self.cores._cores.items():
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config["cores"][name] = instance.to_config()
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if self.interface:
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if isinstance(self.interface, UARTInterface):
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config["uart"] = self.interface.to_config()
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if isinstance(self.interface, EthernetInterface):
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config["ethernet"] = self.interface.to_config()
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import yaml
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with open(path, "w") as f:
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yaml.dump(config, f, default_flow_style=False)
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