34 lines
682 B
Systemverilog
34 lines
682 B
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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module top_level (
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input wire clk,
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input wire btnc,
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input wire btnu,
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input wire [15:0] sw,
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output logic [15:0] led,
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input wire uart_txd_in,
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output logic uart_rxd_out
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);
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// Signal Generator
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logic [7:0] count;
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always_ff @(posedge clk) count <= count + 1;
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// ILA
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// later make this a #ILA that gets loaded from a svh file that the python script generates
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ila ila(
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.clk(clk),
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.rst(btnc),
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.larry(count[0]),
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.curly(count[1]),
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.moe(count[2]),
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.shemp(count[5:3]),
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.rxd(uart_txd_in),
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.txd(uart_rxd_out));
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endmodule
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`default_nettype wire |