325 lines
8.4 KiB
Systemverilog
325 lines
8.4 KiB
Systemverilog
`default_nettype none
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`define CP 10
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`define HCP 5
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task read_reg (
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input [15:0] addr,
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output [15:0] data
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);
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logic_analyzer_tb.tb_la_addr = addr;
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logic_analyzer_tb.tb_la_rw = 0;
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logic_analyzer_tb.tb_la_valid = 1;
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#`CP
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logic_analyzer_tb.tb_la_valid = 0;
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while (!logic_analyzer_tb.la_tb_valid) #`CP;
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data = logic_analyzer_tb.la_tb_rdata;
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endtask
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task write_reg(
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input [15:0] addr,
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input [15:0] data
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);
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logic_analyzer_tb.tb_la_addr = addr;
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logic_analyzer_tb.tb_la_wdata = data;
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logic_analyzer_tb.tb_la_rw = 1;
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logic_analyzer_tb.tb_la_valid = 1;
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#`CP
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logic_analyzer_tb.tb_la_valid = 0;
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while (!logic_analyzer_tb.la_tb_valid) #`CP;
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endtask
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task read_all_reg();
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for(int i = 0; i < (logic_analyzer_tb.la.sample_mem.BASE_ADDR + logic_analyzer_tb.la.SAMPLE_DEPTH); i++) begin
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if(i == logic_analyzer_tb.la.fsm.BASE_ADDR) $display(" -> FSM MEMORY");
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if(i == logic_analyzer_tb.la.trig_blk.BASE_ADDR) $display(" -> TRIG BLK MEMORY");
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if(i == logic_analyzer_tb.la.sample_mem.BASE_ADDR) $display(" -> SAMPLE MEM MEMORY");
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read_reg(i, logic_analyzer_tb.read_value);
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$display(" -> addr: 0x%h rdata: 0x%b", i, logic_analyzer_tb.read_value);
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end
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endtask
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module logic_analyzer_tb;
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// boilerplate
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logic clk;
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integer test_num;
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// signal generator
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logic larry;
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logic curly;
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logic moe;
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logic [3:0] shemp;
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// tb -> la bus
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logic [15:0] tb_la_addr;
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logic [15:0] tb_la_wdata;
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logic [15:0] tb_la_rdata;
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logic tb_la_rw;
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logic tb_la_valid;
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// la -> tb bus
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logic [15:0] la_tb_addr;
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logic [15:0] la_tb_wdata;
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logic [15:0] la_tb_rdata;
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logic la_tb_rw;
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logic la_tb_valid;
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logic_analyzer #(.BASE_ADDR(0), .SAMPLE_DEPTH(128)) la(
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.clk(clk),
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// probes
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.larry(larry),
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.curly(curly),
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.moe(moe),
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.shemp(shemp),
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// input port
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.addr_i(tb_la_addr),
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.wdata_i(tb_la_wdata),
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.rdata_i(tb_la_rdata),
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.rw_i(tb_la_rw),
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.valid_i(tb_la_valid),
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// output port
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.addr_o(la_tb_addr),
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.wdata_o(la_tb_wdata),
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.rdata_o(la_tb_rdata),
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.rw_o(la_tb_rw),
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.valid_o(la_tb_valid));
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always begin
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#`HCP
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clk = !clk;
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end
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reg [15:0] read_value;
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initial begin
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$dumpfile("logic_analyzer_tb.vcd");
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$dumpvars(0, logic_analyzer_tb);
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// setup and reset
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clk = 0;
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test_num = 0;
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tb_la_addr = 0;
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tb_la_rdata = 0;
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tb_la_wdata = 0;
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tb_la_rw = 0;
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tb_la_valid = 0;
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larry = 0;
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curly = 0;
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moe = 0;
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shemp = 0;
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#`HCP
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#(10*`CP);
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/* ==== Test 1 Begin ==== */
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$display("\n=== test 1: read state register ===");
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test_num = 1;
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read_reg(0, read_value);
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$display(" -> read 0x%h from state reg (addr 0x0000)", read_value);
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#(10*`CP);
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/* ==== Test 1 End ==== */
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/* ==== Test 2 Begin ==== */
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$display("\n=== test 2: write to state register and verify ===");
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test_num = 2;
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write_reg(0, 5);
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$display(" -> wrote 0x0005 to state reg (addr 0x0000)");
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read_reg(0, read_value);
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$display(" -> read 0x%h from state reg (addr 0x0000)", read_value);
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write_reg(0, 0);
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$display(" -> wrote 0x0000 to state reg (addr 0x0000)");
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read_reg(0, read_value);
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$display(" -> read 0x%h from state reg (addr 0x0000)", la_tb_rdata);
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#(10*`CP);
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/* ==== Test 2 End ==== */
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/* ==== Test 3 Begin ==== */
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$display("\n=== test 3: write to trigger_loc register and verify ===");
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test_num = 3;
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write_reg(1, -16'sd69);
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$display(" -> wrote -0d69 to trigger_loc reg (addr 0x0001)");
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read_reg(1, read_value);
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$display(" -> read 0d%d from trigger_loc reg (addr 0x0001)", $signed(read_value));
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write_reg(1, 0);
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$display(" -> wrote 0x0000 to trigger_loc reg (addr 0x0001)");
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read_reg(1, read_value);
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$display(" -> read 0x%h from trigger_loc reg (addr 0x0001)", $signed(read_value));
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#(10*`CP);
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/* ==== Test 3 End ==== */
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/* ==== Test 4 Begin ==== */
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$display("\n=== test 4: configure larry_op for equality and verify ===");
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test_num = 4;
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write_reg(2, 8);
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$display(" -> wrote 0x0008 to larry_op reg (addr 0x0002)");
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read_reg(2, read_value);
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$display(" -> read 0x%h from larry_op reg (addr 0x0002)", read_value);
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#(10*`CP);
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/* ==== Test 4 End ==== */
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/* ==== Test 5 Begin ==== */
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$display("\n=== test 5: write 0x0001 to larry_arg register and verify ===");
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test_num = 5;
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write_reg(3, 1);
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$display(" -> wrote 0x0001 to larry_arg reg (addr 0x0003)");
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read_reg(3, read_value);
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$display(" -> read 0x%h from larry_arg reg (addr 0x0003)", read_value);
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#(10*`CP);
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/* ==== Test 5 End ==== */
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/* ==== Test 6 Begin ==== */
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$display("\n=== test 6: set larry = 1, verify core does not trigger ===");
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test_num = 6;
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$display(" -> set larry = 1");
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larry = 1;
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$display(" -> la core is in state 0x%h", la.fsm.state);
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$display(" -> wait a clock cycle");
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#`CP
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$display(" -> la core is in state 0x%h", la.fsm.state);
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$display(" -> set larry = 0");
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larry = 0;
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#(10*`CP);
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/* ==== Test 6 End ==== */
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/* ==== Test 7 Begin ==== */
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$display("\n=== test 7: set larry = 1, verify core does trigger ===");
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test_num = 7;
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write_reg(0, 1);
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$display(" -> wrote 0x0001 to state reg (addr 0x0000)");
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#`CP
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$display(" -> set larry = 1");
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larry = 1;
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// read
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$display(" -> la core is in state 0x%h", la.fsm.state);
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$display(" -> wait a clock cycle");
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#`CP
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$display(" -> la core is in state 0x%h", la.fsm.state);
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// run until the FILLED state is reached
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$display(" -> wait until FILLED state is reached");
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while (la.fsm.state != la.fsm.FILLED) begin
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{larry, curly, moe, shemp} = {larry, curly, moe, shemp} + 1;
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#`CP;
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end
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$display(" -> read from sample memory:");
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read_all_reg();
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#(200*`CP);
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/* ==== Test 7 End ==== */
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/* ==== Test 8 Begin ==== */
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$display("\n=== test 8: change trigger to fire on shemp > 3, and verify ===");
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test_num = 8;
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write_reg(8, 6);
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$display(" -> wrote 0x0006 to shemp_op reg (addr 0x0008)");
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read_reg(8, read_value);
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$display(" -> read 0x%h from shemp_op reg (addr 0x0008)", la_tb_rdata);
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write_reg(9, 3);
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$display(" -> wrote 0x0003 to shemp_arg reg (addr 0x0009)");
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read_reg(9, read_value);
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$display(" -> read 0x%h from shemp_arg reg (addr 0x0009)", read_value);
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#(10*`CP);
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/* ==== Test 8 End ==== */
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/* ==== Test 9 Begin ==== */
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$display("\n=== test 9: set state machine to IDLE, verify core does not trigger ===");
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test_num = 9;
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read_reg(0, read_value);
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$display(" -> read 0x%h from state reg (addr 0x0000)", read_value);
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write_reg(0, 0);
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$display(" -> wrote 0x0000 to state reg (addr 0x0000)");
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read_reg(0, read_value);
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$display(" -> read 0x%h from state reg (addr 0x0000)", read_value);
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/* ==== Test 9 End ==== */
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/* ==== Test 10 Begin ==== */
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$display("\n=== test 10: set shemp = 4, verify core does trigger ===");
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test_num = 10;
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larry = 0;
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curly = 0;
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moe = 0;
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shemp = 0;
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write_reg(0, 1);
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$display(" -> wrote 0x0001 to state reg (addr 0x0000)");
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shemp = 4;
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$display(" -> set shemp = 4");
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// run until the FILLED state is reached
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$display(" -> wait until FILLED state is reached");
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while (la.fsm.state != la.fsm.FILLED) begin
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{larry, curly, moe, shemp} = {larry, curly, moe, shemp} + 2;
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#`CP;
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end
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$display(" -> read from sample memory:");
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read_all_reg();
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#(200*`CP);
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/* ==== Test 10 End ==== */
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$finish();
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end
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endmodule
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`default_nettype wire |