114 lines
2.1 KiB
Systemverilog
114 lines
2.1 KiB
Systemverilog
`default_nettype none
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`define CP 10
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`define HCP 5
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module io_core_tb;
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// boilerplate
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logic clk;
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integer test_num;
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// inputs
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logic picard;
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logic [6:0] data;
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logic [9:0] laforge;
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logic troi;
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// outputs
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logic kirk;
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logic [4:0] spock;
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logic [2:0] uhura;
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logic chekov;
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// tb -> io bus
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logic [15:0] tb_io_addr;
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logic [15:0] tb_io_wdata;
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logic [15:0] tb_io_rdata;
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logic tb_io_rw;
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logic tb_io_valid;
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// la -> io bus
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logic [15:0] la_tb_addr;
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logic [15:0] la_tb_wdata;
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logic [15:0] la_tb_rdata;
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logic la_tb_rw;
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logic la_tb_valid;
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io_core #(.BASE_ADDR(0), .SAMPLE_DEPTH(128)) io(
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.clk(clk),
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// inputs
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.picard(picard),
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.data(data),
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.laforge(laforge),
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.troi(troi),
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// outputs
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.kirk(kirk),
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.spock(spock),
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.uhura(uhura),
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.chekov(chekov),
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// input port
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.addr_i(tb_io_addr),
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.wdata_i(tb_io_wdata),
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.rdata_i(tb_io_rdata),
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.rw_i(tb_io_rw),
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.valid_i(tb_io_valid),
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// output port
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.addr_o(la_tb_addr),
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.wdata_o(la_tb_wdata),
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.rdata_o(la_tb_rdata),
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.rw_o(la_tb_rw),
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.valid_o(la_tb_valid));
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always begin
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#`HCP
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clk = !clk;
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end
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initial begin
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$dumpfile("io_core_tb.vcd");
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$dumpvars(0, io_core_tb);
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// setup and reset
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clk = 0;
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test_num = 0;
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tb_io_addr = 0;
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tb_io_rdata = 0;
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tb_io_wdata = 0;
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tb_io_rw = 0;
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tb_io_valid = 0;
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picard = 0;
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data = 0;
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laforge = 0;
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troi = 0;
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#`HCP
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#(10*`CP);
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/* ==== Test 1 Begin ==== */
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$display("\n=== test 1: read state register ===");
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test_num = 1;
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tb_io_addr = 0;
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tb_io_valid = 1;
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#`CP
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tb_io_valid = 0;
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while (!la_tb_valid) #`CP;
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$display(" -> read 0x%h from state reg (addr 0x0000)", la_tb_rdata);
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#(10*`CP);
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/* ==== Test 1 End ==== */
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$finish();
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end
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endmodule
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`default_nettype wire |