71 lines
916 B
Systemverilog
71 lines
916 B
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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module fifo_tb();
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logic clk;
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logic rst;
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logic [7:0] in;
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logic in_valid;
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logic out_req;
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logic [7:0] out;
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logic [11:0] size;
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logic empty;
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logic full;
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fifo uut (
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.clk(clk),
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.bram_rst(rst),
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.in(in),
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.in_valid(in_valid),
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.out_req(out_req),
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.out(out),
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.size(size),
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.empty(empty),
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.full(full));
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always begin
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#5;
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clk = !clk;
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end
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initial begin
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$dumpfile("fifo.vcd");
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$dumpvars(0, fifo_tb);
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clk = 0;
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rst = 1;
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in = 0;
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in_valid = 0;
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out_req = 0;
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#10;
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rst = 0;
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#10;
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// try and load some data, make sure counter increases
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in_valid = 1;
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for(int i=0; i < 4097; i++) begin
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in = i;
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#10;
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end
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in_valid = 0;
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// try and read out said data
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out_req = 1;
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for(int i=0; i < 4097; i++) begin
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$display("%h", out);
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#10;
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end
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$finish();
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end
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endmodule
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`default_nettype wire
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