75 lines
1.4 KiB
Systemverilog
75 lines
1.4 KiB
Systemverilog
`default_nettype none
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`timescale 1ns/1ps
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`define CP 10
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`define HCP 5
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module bit_fifo_tb;
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//boilerplate
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logic clk;
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integer test_num;
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always begin
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#`HCP
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clk = !clk;
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end
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parameter IWIDTH = 3;
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parameter OWIDTH = 7;
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logic en;
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logic [IWIDTH-1:0] in;
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logic in_valid;
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logic [OWIDTH-1:0] out;
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logic out_valid;
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bit_fifo #(.IWIDTH(IWIDTH), .OWIDTH(OWIDTH)) bfifo (
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.clk(clk),
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.en(en),
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.in(in),
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.in_valid(in_valid),
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.out(out),
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.out_valid(out_valid));
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initial begin
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$dumpfile("bit_fifo_tb.vcd");
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$dumpvars(0, bit_fifo_tb);
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// setup and reset
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clk = 0;
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test_num = 0;
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en = 0;
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in_valid = 0;
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in = 0;
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#`HCP
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#(10*`CP);
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/* ==== Test 1 Begin ==== */
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$display("\n=== test 1: make sure invalid data isn't added to buffer ===");
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test_num = 1;
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en = 1;
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#(10*`CP);
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en = 0;
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/* ==== Test 1 End ==== */
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/* ==== Test 2 Begin ==== */
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$display("\n=== test 2: just throw bits at it! ===");
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test_num = 1;
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en = 1;
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in_valid = 1;
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in = 3'b101;
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#(10*`CP);
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in_valid = 0;
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en = 0;
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#(10*`CP);
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/* ==== Test 2 End ==== */
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$finish();
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end
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endmodule
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`default_nettype wire |