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<h1>Block Memory Core</h1>
<h2 id="overview">Overview</h2>
<p>Block Memory (also called Block RAM, or BRAM) is the de facto means of storing data on FPGAs when the space needed exceeds a few registers. As a result, Manta provides a Block Memory core, which instantiates a dual-port BRAM on the FPGA. One port is provided to the host, and the other is connected to your logic with the standard BRAM interface (<code>addr</code>, <code>din</code>, <code>dout</code>, <code>wea</code>). This allows the host to provide reasonably large amounts of data to user logic - or the other way around, or a mix of both!</p>
<p>This is a very, very simple task - and while configuration is straightforward, there are a few caveats. More on both topics below:</p>
<h2 id="configuration">Configuration</h2>
<p>Just like the rest of the cores, the Block Memory core is configured via an entry in a project's configuration file. This is easiest to show by example:</p>
<div class="language-yaml highlight"><pre><span></span><code><span id="__span-0-1"><a id="__codelineno-0-1" name="__codelineno-0-1" href="#__codelineno-0-1"></a><span class="nn">---</span>
</span><span id="__span-0-2"><a id="__codelineno-0-2" name="__codelineno-0-2" href="#__codelineno-0-2"></a><span class="nt">cores</span><span class="p">:</span>
</span><span id="__span-0-3"><a id="__codelineno-0-3" name="__codelineno-0-3" href="#__codelineno-0-3"></a><span class="w"> </span><span class="nt">my_block_memory</span><span class="p">:</span>
</span><span id="__span-0-4"><a id="__codelineno-0-4" name="__codelineno-0-4" href="#__codelineno-0-4"></a><span class="w"> </span><span class="nt">type</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">block_memory</span>
</span><span id="__span-0-5"><a id="__codelineno-0-5" name="__codelineno-0-5" href="#__codelineno-0-5"></a><span class="w"> </span><span class="nt">width</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">12</span>
</span><span id="__span-0-6"><a id="__codelineno-0-6" name="__codelineno-0-6" href="#__codelineno-0-6"></a><span class="w"> </span><span class="nt">depth</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">16384</span>
</span></code></pre></div>
<p>There's a few parameters that get configured here, including:</p>
<ul>
<li><code>name</code>: The name of the Block Memory core. This name is used to reference the core when working with the API, and can be whatever you'd like.</li>
<li><code>type</code>: This denotes that this is a Block Memory core. All cores contain a <code>type</code> field, which must be set to <code>block_memory</code> to be recognized as an Block Memory core.</li>
</ul>
<h3 id="dimensions">Dimensions</h3>
<p>The dimensions of the block memory are specified in the config file with the <code>width</code> and <code>depth</code> entries.</p>
<p>Manta won't impose any limit on the width or depth of the block memory you instantiate, but since Manta instantiates BRAM primitives on the FPGA, you will be limited by what your FPGA can support. It helps to know your particular FPGA's architecture here.</p>
<p>If your BRAM is more than 16 bits wide, check out the section on <a href="#synchronicity">Synchronicity</a> and make sure your project will tolerate how Manta writes to the block memory.</p>
<h3 id="python-api">Python API</h3>
<p>The Block Memory core functionality is stored in the <code>Manta.IOCore</code> and <code>Manta.IOCoreProbe</code> classes in <a href="https://github.com/fischermoseley/manta/blob/main/src/manta/io_core/__init__.py">src/manta/io_core/__init__.py</a>, and it may be controlled with the two functions:</p>
<p>Just like with the other cores, interfacing with the BRAM with the Python API is simple:</p>
<div class="language-python highlight"><pre><span></span><code><span id="__span-1-1"><a id="__codelineno-1-1" name="__codelineno-1-1" href="#__codelineno-1-1"></a><span class="kn">from</span> <span class="nn">manta</span> <span class="kn">import</span> <span class="n">Manta</span>
</span><span id="__span-1-2"><a id="__codelineno-1-2" name="__codelineno-1-2" href="#__codelineno-1-2"></a><span class="n">m</span> <span class="o">=</span> <span class="n">manta</span><span class="p">(</span><span class="s1">&#39;manta.yaml&#39;</span><span class="p">)</span>
</span><span id="__span-1-3"><a id="__codelineno-1-3" name="__codelineno-1-3" href="#__codelineno-1-3"></a>
</span><span id="__span-1-4"><a id="__codelineno-1-4" name="__codelineno-1-4" href="#__codelineno-1-4"></a><span class="n">m</span><span class="o">.</span><span class="n">my_block_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addr</span><span class="o">=</span><span class="mi">38</span><span class="p">,</span> <span class="n">data</span><span class="o">=</span><span class="mi">600</span><span class="p">)</span>
</span><span id="__span-1-5"><a id="__codelineno-1-5" name="__codelineno-1-5" href="#__codelineno-1-5"></a><span class="n">m</span><span class="o">.</span><span class="n">my_block_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addr</span><span class="o">=</span><span class="mh">0x1234</span><span class="p">,</span> <span class="n">data</span> <span class="o">=</span> <span class="mb">0b100011101011</span><span class="p">)</span>
</span><span id="__span-1-6"><a id="__codelineno-1-6" name="__codelineno-1-6" href="#__codelineno-1-6"></a><span class="n">m</span><span class="o">.</span><span class="n">my_block_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="mh">0x0612</span><span class="p">,</span> <span class="mh">0x2001</span><span class="p">)</span>
</span><span id="__span-1-7"><a id="__codelineno-1-7" name="__codelineno-1-7" href="#__codelineno-1-7"></a>
</span><span id="__span-1-8"><a id="__codelineno-1-8" name="__codelineno-1-8" href="#__codelineno-1-8"></a><span class="n">foo</span> <span class="o">=</span> <span class="n">m</span><span class="o">.</span><span class="n">my_block_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addr</span><span class="o">=</span><span class="mi">38</span><span class="p">)</span>
</span><span id="__span-1-9"><a id="__codelineno-1-9" name="__codelineno-1-9" href="#__codelineno-1-9"></a><span class="n">foo</span> <span class="o">=</span> <span class="n">m</span><span class="o">.</span><span class="n">my_block_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addr</span><span class="o">=</span><span class="mi">1234</span><span class="p">)</span>
</span><span id="__span-1-10"><a id="__codelineno-1-10" name="__codelineno-1-10" href="#__codelineno-1-10"></a><span class="n">foo</span> <span class="o">=</span> <span class="n">m</span><span class="o">.</span><span class="n">my_block_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="mh">0x0612</span><span class="p">)</span>
</span></code></pre></div>
<p>Reading/writing in batches is also supported. This is recommended where possible, as reads are massively sped up by performing them in bulk:</p>
<div class="language-python highlight"><pre><span></span><code><span id="__span-2-1"><a id="__codelineno-2-1" name="__codelineno-2-1" href="#__codelineno-2-1"></a><span class="n">addrs</span> <span class="o">=</span> <span class="nb">list</span><span class="p">(</span><span class="nb">range</span><span class="p">(</span><span class="mi">0</span><span class="p">,</span> <span class="mi">1234</span><span class="p">))</span>
</span><span id="__span-2-2"><a id="__codelineno-2-2" name="__codelineno-2-2" href="#__codelineno-2-2"></a><span class="n">datas</span> <span class="o">=</span> <span class="nb">list</span><span class="p">(</span><span class="nb">range</span><span class="p">(</span><span class="mi">1234</span><span class="p">,</span> <span class="mi">2468</span><span class="p">))</span>
</span><span id="__span-2-3"><a id="__codelineno-2-3" name="__codelineno-2-3" href="#__codelineno-2-3"></a><span class="n">m</span><span class="o">.</span><span class="n">my_block_memory</span><span class="o">.</span><span class="n">write</span><span class="p">(</span><span class="n">addrs</span><span class="p">,</span> <span class="n">datas</span><span class="p">)</span>
</span><span id="__span-2-4"><a id="__codelineno-2-4" name="__codelineno-2-4" href="#__codelineno-2-4"></a>
</span><span id="__span-2-5"><a id="__codelineno-2-5" name="__codelineno-2-5" href="#__codelineno-2-5"></a><span class="n">foo</span> <span class="o">=</span> <span class="n">m</span><span class="o">.</span><span class="n">my_block_memory</span><span class="o">.</span><span class="n">read</span><span class="p">(</span><span class="n">addrs</span><span class="p">)</span>
</span></code></pre></div>
<h3 id="examples">Examples</h3>
<p>A Block Memory core is used in the <a href="https://github.com/fischermoseley/manta/blob/main/examples/nexys_a7/video_sprite">video_sprite</a> example. This uses the core to store a 128x128 image sprite in 12-bit color, and outputs it to a VGA display at 1024x768. The sprite contents can be filled with an arbitrary image using the <a href="https://github.com/fischermoseley/manta/blob/main/examples/nexys_a7/video_sprite/send_image.py">send_image.py</a> python script.</p>
<h2 id="under-the-hood">Under the Hood</h2>
<p>Each Block Memory core is actually a set of 16-bit wide BRAMs with their ports concatenated together, with any spare bits masked off. Here's a diagram:</p>
<p><img alt="" src="../assets/block_memory_architecture.png" /></p>
<p>This has one major consequence: if the core doesn't have a width that's an exact multiple of 16, synthesis engines (Vivado in particular) will throw some warnings as they optimize out the unused bits. This is expected behavior, and while the warnings are a little annoying, not having to manually deal with the unused bits simplifies the implementation immensely. No Python is needed to generate the core, and it'll configure itself just based on Verilog parameters. This turns the block memory core from a complicated conditionally-instantiated beast to a simple ~<em>100 line</em> <a href="https://github.com/fischermoseley/manta/blob/main/src/manta/block_memory.v">Verilog file</a>.</p>
<h3 id="address-assignment">Address Assignment</h3>
<p>Since each <span class="arithmatex">\(n\)</span>-bit wide block memory is actually <span class="arithmatex">\(ceil(n/16)\)</span> BRAMs under the hood, addressing the BRAMs correctly from Manta's internal bus is important. BRAMs are organized such that each 16-bit slice of a <span class="arithmatex">\(N\)</span>-bit word in the Block Memory core are placed next to each other in bus address space. For instance, a 34-bit wide block memory would exist on Manta's internal bus as:</p>
<table>
<thead>
<tr>
<th>Bus Address Space</th>
<th>BRAM Address Space</th>
</tr>
</thead>
<tbody>
<tr>
<td>BASE_ADDR + 0</td>
<td>address 0, bits 0-15</td>
</tr>
<tr>
<td>BASE_ADDR + 1</td>
<td>address 0, bits 16-31</td>
</tr>
<tr>
<td>BASE_ADDR + 2</td>
<td>address 0, bits 32-33</td>
</tr>
<tr>
<td>BASE_ADDR + 3</td>
<td>address 1, bits 0-15</td>
</tr>
<tr>
<td>BASE_ADDR + 4</td>
<td>address 1, bits 16-31</td>
</tr>
<tr>
<td>BASE_ADDR + 5</td>
<td>address 1, bits 32-33</td>
</tr>
</tbody>
</table>
<p>...and so on.</p>
<h3 id="synchronicity">Synchronicity</h3>
<p>Since Manta's <a href="../system_architecture">data bus</a> is only 16-bits wide, it's only possible to manipulate the BRAM core in 16-bit increments. This means that if you have a BRAM that's ≤16 bits wide, you'll only need to issue a single bus transaction to read/write one entry in the BRAM. However, if you have a BRAM that's ≥16 bits wide, you'll need to issue a bus transaction to update each 16-bit slice of it. For instance, updating a single entry in a 33-bit wide BRAM would require sending 3 messages to the FPGA: one for bits 1-16, another for bits 17-32, and one for bit 33. If your application expects each BRAM entry to update instantaneously, this could be problematic.</p>
<p>There's a few different ways to solve this - you could use an IO core to signal when a BRAM's contents or valid - or you could ping-pong between two BRAMs while one is being modified. The choice is yours, and Manta makes no attempt to presribe any particular approach.</p>
<p>Lastly, the interface you use (and to a lesser extent, your operating system) will determine the space between bus transactions. For instance, 100Mbit Ethernet is a thousand times faster than 115200bps UART, so the time where the BRAM is invalid is a thousand times smaller.</p>
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