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32 KiB
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Architecture
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Open Source Tools
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LiteScope
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ZipCPU Debugger
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<a href="#opal-kelly-frontpanel-sdk" class="md-nav__link">
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<span class="md-ellipsis">
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Opal Kelly FrontPanel SDK
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<a href="#matlab-fpga-data-capture" class="md-nav__link">
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MATLAB FPGA Data Capture
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Cores
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IO Core
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Logic Analyzer Core
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Memory Core
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UART Interface
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Ethernet Interface
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LiteScope
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GateMate ILA
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ZipCPU Debugger
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Xilinx Integrated Logic Analzyer
|
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Xilinx Virtual IO
|
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Intel Signal Tap
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Intel In-System Sources and Probes
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Lattice Reveal
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|
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<a href="#opal-kelly-frontpanel-sdk" class="md-nav__link">
|
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<span class="md-ellipsis">
|
||
Opal Kelly FrontPanel SDK
|
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|
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MATLAB FPGA Data Capture
|
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|
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|
||
|
||
|
||
|
||
<h1>Similar Tools</h1>
|
||
|
||
<p>This page contains a list of tools similar to Manta, either in function or intention. This is meant to provide a useful comparison to other tools that you may be more familiar with, in hopes of a smoother experience integrating Manta into your project.</p>
|
||
<p>That said, Manta is by no means feature-complete, and there may be an alternative tool listed on this page that better fits your use case. If that is the case, we encourage you to use that tool (although do consider filing a <a href="https://github.com/fischermoseley/manta/issues/new">feature request</a> - we’d love to hear about your workflow!). The goal of this project is to make working with FPGAs easier, and maintaining this list serves that end.</p>
|
||
<p>If you're aware of a tool missing from this list, please <a href="https://github.com/fischermoseley/manta/issues/new">let us know</a>!</p>
|
||
<h2 id="open-source-tools">Open Source Tools</h2>
|
||
<h3 id="litescope">LiteScope</h3>
|
||
<p>An embedded logic analyzer written in Migen, primarily for use in LiteX SoC designs. Also includes IO peek and poke, as well as UART, Ethernet, and PCIe interfaces with a host machine. Includes VCD, Sigrok, CSV, and Python data export.</p>
|
||
<ul>
|
||
<li><a href="https://github.com/enjoy-digital/litescope">Source Code</a></li>
|
||
<li><a href="https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC">Documentation</a></li>
|
||
</ul>
|
||
<h3 id="gatemate-ila">GateMate ILA</h3>
|
||
<p>An embedded logic analyzer written in Verilog, targeting the GateMate FPGA family from Colonge Chip and the Yosys/NextPNR toolchain. Communication between the host and FPGA is accomplished with SPI, via a FT232 or FT2232 used as a USB-SPI adapter. GateMate is inteneded to be used with GTKWave, so the tool generates <code>.gtkw</code> files in addition to VCD files.</p>
|
||
<ul>
|
||
<li><a href="https://github.com/colognechip/gatemate_ila">Source Code</a></li>
|
||
</ul>
|
||
<h3 id="zipcpu-debugger">ZipCPU Debugger</h3>
|
||
<p>A set of embedded debugging modules written by Dan Gisselquist of ZipCPU fame. Communication between the host and FPGA is accomplished with UART, and control of the debugger is performed with a C++ API on the host. A wishbone interface is provided on the FPGA side to connect to other Wishbone-based debugging tools that can provide control of user registers, block RAM, and an embedded logic analyzer. Supports dumping of signals to a VCD file.</p>
|
||
<ul>
|
||
<li><a href="https://github.com/ZipCPU/dbgbus">Source Code</a></li>
|
||
<li><a href="https://zipcpu.com/topics.html">Documentation</a>, under the <em>How to Debug an FPGA</em> section.</li>
|
||
</ul>
|
||
<h2 id="commercial-tools">Commercial Tools</h2>
|
||
<h3 id="xilinx-integrated-logic-analzyer">Xilinx Integrated Logic Analzyer</h3>
|
||
<p>An embedded logic analyzer for Xilinx FPGAs, provided as part of the Xilinx Vivado development suite. Communication between the host and FPGA is accomplished with JTAG, typically running over a USB cable to the device. Includes an integrated waveform viewer, and VCD and CSV export. Also supports a JTAG-to-AXI mode, which integrates well with Xilinx IP, which uses primarily AXI. Also integrates with the ChipScoPy API, which allows for Python control of the ILA on Versal devices. The ILA was previously known as ChipScope in earlier versions of Vivado.</p>
|
||
<ul>
|
||
<li><a href="https://docs.xilinx.com/v/u/en-US/pg172-ila">ILA Documentation</a></li>
|
||
<li><a href="https://docs.xilinx.com/r/en-US/ug936-vivado-tutorial-programming-debugging/Using-the-Vivado-Logic-Analyzer-to-Debug-Hardware">ILA User's Guide</a></li>
|
||
<li><a href="https://github.com/Xilinx/chipscopy">ChipScoPy API</a></li>
|
||
</ul>
|
||
<h3 id="xilinx-virtual-io">Xilinx Virtual IO</h3>
|
||
<p>A tool for reading and writing to individual registers on the FPGA, provided as part of the Xilinx Vivado development suite. Just like the ILA, communication between the host and FPGA is done over JTAG. Control over the registers is done through the Vivado GUI or through the Tcl interpreter. In the case of Versal devices, the ChipScoPy API can also control the registers.</p>
|
||
<ul>
|
||
<li><a href="https://docs.xilinx.com/v/u/en-US/pg159-vio">Virtual IO Documentation</a></li>
|
||
<li><a href="https://github.com/Xilinx/chipscopy">ChipScoPy API</a></li>
|
||
</ul>
|
||
<h3 id="intel-signal-tap">Intel Signal Tap</h3>
|
||
<p>An embedded logic analyzer for Intel/Altera FPGAs, provided as part of the Quartus development suite. Communication between the host and FPGA is accomplished with JTAG, and a programmable interface is provided via Tcl. Signal Tap is notable for providing a significant amount of configurability in the trigger conditions, and provides a small scripting language called <em>Trigger Flow</em> that allows users to define triggers as state machines. Signal Tap also allows for <em>Simulation-Aware nodes</em>, which allows for running simulations with data captured from the real world. At the time of writing, this feature is only available in the most recent and full-featured version of the Quartus suite, Quartus Prime Pro Edition 22.4.</p>
|
||
<ul>
|
||
<li><a href="https://www.intel.com/content/www/us/en/docs/programmable/683552/18-1/design-debugging-with-the-logic-analyzer-69524.html">Documentation</a></li>
|
||
</ul>
|
||
<h3 id="intel-in-system-sources-and-probes">Intel In-System Sources and Probes</h3>
|
||
<p>A tool for reading and writing to individual registers on the FPGA, provided for Intel/Altera FPGAs as part of the Quartus development suite. Just like Signal Tap, communication between the host and FPGA is accomplished with JTAG.</p>
|
||
<ul>
|
||
<li><a href="https://www.intel.com/content/www/us/en/docs/programmable/683552/18-1/design-debugging-using-in-system-sources-45607.html">Documentation</a></li>
|
||
</ul>
|
||
<h3 id="lattice-reveal">Lattice Reveal</h3>
|
||
<p>An embedded logic analyzer for Lattice FPGAs, provided as part of the Diamond development suite. Communication between the host and FPGA is accomplished with JTAG. Reveal is notable for providing a significant amount of configurability in the trigger conditions, and supports trigger conditions formed with a mix of combinational and sequential logic. Reveal also provides special support for Wishbone buses, and for controlling SERDES modules on ECP5 devices.</p>
|
||
<ul>
|
||
<li><a href="https://www.latticesemi.com/~/media/328D471BF2C74EB1907832FAA6FB344B.ashx">Documentation</a></li>
|
||
</ul>
|
||
<h3 id="opal-kelly-frontpanel-sdk">Opal Kelly FrontPanel SDK</h3>
|
||
<p>Unlike other entries in this list, Opal Kelly's FrontPanel SDK is not marketed as a debugger (although it can be used as such). Instead, it's designed to provide a host computer with a real time interface to FPGA signals, and present them on a graphical “front panel". These front panels exist as a GUI window on the host, and contain buttons, knobs, and indicators, much like a LabVIEW virtual instrument. Communication between the host and FPGA is accomplished with either USB or PCIe. Bindings for hosts running Windows, macOS, and Linux are provided, and target C, C++, C#, Python, Java, Ruby, and MATLAB. The FrontPanel SDK differs from other debuggers in that it provides a skeleton module into which the user logic is instantiated, instead of being instantiated inside the user's logic.</p>
|
||
<ul>
|
||
<li><a href="https://docs.opalkelly.com/fpsdk/">Documentation</a></li>
|
||
<li><a href="https://assets00.opalkelly.com/library/FrontPanel-UM.pdf">User's Guide</a></li>
|
||
</ul>
|
||
<h3 id="matlab-fpga-data-capture">MATLAB FPGA Data Capture</h3>
|
||
<p>An embedded logic analyzer for Xilinx and Altera FPGAs, provided as part of MATLAB. Communication between the host and FPGA is accomplished with JTAG, but Ethernet is supported for Xilinx FPGAs. Notably, this tool allows for data to be captured and used directly inside MATLAB, which also includes a framework for FPGA-in-the-loop testing. It also provides an AXI manager IP block that allows for reads and writes to an AXI memory map from MATLAB. This IP supports PCI Express on Xilinx FPGAs, in addition to JTAG and Ethernet.</p>
|
||
<ul>
|
||
<li><a href="https://www.mathworks.com/help/hdlverifier/fpga-data-capture-xilinx.html">Documentation</a></li>
|
||
</ul>
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
</article>
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