1068 lines
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Cores
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Cores
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IO Core
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Logic Analyzer Core
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Interfaces
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UART Interface
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Ethernet Interface
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<h1>Ethernet Interface</h1>
|
||
|
||
<h2 id="overview">Overview</h2>
|
||
<p>For applications where UART is too slow or isn't available, Manta provides the option to run over Ethernet. This is done via UDP, so the FPGA can be anywhere on the same network as the host machine - as opposed to MAC-based Ethernet interfaces, which usually require a point-to-point network connection between the FPGA and the host. Although UDP does not guaruntee reliable, in-order packet delivery, this generally tends to be the case on uncongested networks. In the future, Manta will enforce this at the <a href="https://github.com/fischermoseley/manta/issues/10">application layer</a>.</p>
|
||
<div class="admonition info">
|
||
<p class="admonition-title">Not every device is supported!</p>
|
||
<p>Internally, the Ethernet Interface uses <a href="https://github.com/enjoy-digital/liteeth">LiteEth</a> to generate cross-platform RTL for the FPGA. As a result, the supported devices are loosely restricted to those <a href="https://github.com/enjoy-digital/liteeth?tab=readme-ov-file#-features">supported by LiteEth</a>. If a device you'd like to use isn't on the list, the community would love your help.</p>
|
||
</div>
|
||
<p>Both the <a href="../use_cases">Use Cases</a> page and the repository's <a href="https://github.com/fischermoseley/manta/tree/main/examples">examples</a> folder contain examples of the Ethernet Interface for your reference.</p>
|
||
<h2 id="configuration">Configuration</h2>
|
||
<h3 id="verilog-based-workflows">Verilog-Based Workflows</h3>
|
||
<p>The UART interface is used by adding a <code>ethernet</code> entry at the bottom of the configuration file. This is best shown by example:</p>
|
||
<p><div class="language-yaml highlight"><pre><span></span><code><span id="__span-0-1"><a id="__codelineno-0-1" name="__codelineno-0-1" href="#__codelineno-0-1"></a><span class="nt">ethernet</span><span class="p">:</span>
|
||
</span><span id="__span-0-2"><a id="__codelineno-0-2" name="__codelineno-0-2" href="#__codelineno-0-2"></a><span class="w"> </span><span class="nt">phy</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">LiteEthPHYRMII</span>
|
||
</span><span id="__span-0-3"><a id="__codelineno-0-3" name="__codelineno-0-3" href="#__codelineno-0-3"></a><span class="w"> </span><span class="nt">vendor</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">xilinx</span>
|
||
</span><span id="__span-0-4"><a id="__codelineno-0-4" name="__codelineno-0-4" href="#__codelineno-0-4"></a><span class="w"> </span><span class="nt">toolchain</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">vivado</span>
|
||
</span><span id="__span-0-5"><a id="__codelineno-0-5" name="__codelineno-0-5" href="#__codelineno-0-5"></a>
|
||
</span><span id="__span-0-6"><a id="__codelineno-0-6" name="__codelineno-0-6" href="#__codelineno-0-6"></a><span class="w"> </span><span class="nt">clk_freq</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">50e6</span>
|
||
</span><span id="__span-0-7"><a id="__codelineno-0-7" name="__codelineno-0-7" href="#__codelineno-0-7"></a><span class="w"> </span><span class="nt">refclk_freq</span><span class="p">:</span><span class="w"> </span><span class="l l-Scalar l-Scalar-Plain">50e6</span>
|
||
</span><span id="__span-0-8"><a id="__codelineno-0-8" name="__codelineno-0-8" href="#__codelineno-0-8"></a>
|
||
</span><span id="__span-0-9"><a id="__codelineno-0-9" name="__codelineno-0-9" href="#__codelineno-0-9"></a><span class="w"> </span><span class="nt">fpga_ip_addr</span><span class="p">:</span><span class="w"> </span><span class="s">"192.168.0.110"</span>
|
||
</span><span id="__span-0-10"><a id="__codelineno-0-10" name="__codelineno-0-10" href="#__codelineno-0-10"></a><span class="w"> </span><span class="nt">host_ip_addr</span><span class="p">:</span><span class="w"> </span><span class="s">"192.168.0.100"</span>
|
||
</span></code></pre></div>
|
||
Inside this configuration, the following parameters may be set:</p>
|
||
<ul>
|
||
<li>
|
||
<p><code>phy</code> <em>(required)</em>: The name of the LiteEth PHY class to use. Select the appropriate one from <a href="https://github.com/enjoy-digital/liteeth/blob/b4e28506238c5340f2ade7899c2223424cabd410/liteeth/phy/__init__.py#L25-L45">this list</a> for your FPGA vendor and family.</p>
|
||
</li>
|
||
<li>
|
||
<p><code>vendor</code> <em>(required)</em>: The vendor of your FPGA. Currently only values of <code>xilinx</code> and <code>lattice</code> are supported. This is used to generate (currently unused) timing constraints files.</p>
|
||
</li>
|
||
<li>
|
||
<p><code>toolchain</code> <em>(required)</em>: The toolchain being used. Currently only values of <code>vivado</code> and <code>diamond</code> are supported.</p>
|
||
</li>
|
||
<li>
|
||
<p><code>clk_freq</code> <em>(required)</em>: The frequency of the clock provided to the Manta module on the FPGA, in Hertz (Hz).</p>
|
||
</li>
|
||
<li>
|
||
<p><code>refclk_freq</code> <em>(required)</em>: The frequency of the reference clock to be provided to the Ethernet PHY, in Hertz (Hz). This frequency must match the MII variant used by the PHY, and speed it is being operated at. For instance, a RGMII PHY may be operated at either 125MHz in Gigabit mode, or 25MHz in 100Mbps mode.</p>
|
||
</li>
|
||
<li>
|
||
<p><code>fpga_ip_addr</code> <em>(required)</em>: The IP address the FPGA will attempt to claim. Upon power-on, the FPGA will issue a DHCP request for this IP address. Ping this address after power-on to check if this request was successful, or check your router for a list of connected devices.</p>
|
||
</li>
|
||
<li>
|
||
<p><code>host_ip_addr</code> <em>(required)</em>: The IP address of the host machine, which the FPGA will send packets back to.</p>
|
||
</li>
|
||
<li>
|
||
<p><code>udp_port</code> <em>(optional)</em>: The UDP port to communicate over. Defaults to 2001.</p>
|
||
</li>
|
||
</ul>
|
||
<p>Lastly, any additonal arguments provided in the <code>ethernet</code> section of the config file will be passed to the LiteEth standalone core generator. As a result, the <a href="https://github.com/enjoy-digital/liteeth/tree/master/examples">examples</a> provided by LiteEth may be of some service to you if you're bringing up a different FPGA!</p>
|
||
<div class="admonition warning">
|
||
<p class="admonition-title">LiteEth doesn't always generate its own <code>refclk</code>!</p>
|
||
<p>Although LitEth is built on Migen and LiteX which support PLLs and other clock generation primitives, I haven't seen it instantiate one to synthesize a suitable <code>refclk</code> at the appropriate frequency from the input clock. As a result, for now it's recommended to generate your <code>refclk</code> outside Manta, and then use it to clock your Manta instance.</p>
|
||
</div>
|
||
<h3 id="amaranth-native-designs">Amaranth-Native Designs</h3>
|
||
<p>Since Amaranth modules are Python objects, the configuration of the IO Core is given by the arguments given during initialization. See the documentation for the <code>EthernetInterface</code> <a href="#manta.EthernetInterface">class constructor</a> below, as well as the Amaranth <a href="https://github.com/fischermoseley/manta/tree/main/examples/amaranth">examples</a> in the repo.</p>
|
||
|
||
|
||
<div class="doc doc-object doc-class">
|
||
|
||
|
||
|
||
<h3 id="manta.EthernetInterface" class="doc doc-heading">
|
||
<code class="doc-symbol doc-symbol-heading doc-symbol-class"></code> <span class="doc doc-object-name doc-class-name">manta.EthernetInterface</span>
|
||
|
||
|
||
</h3>
|
||
<div class="language-python doc-signature highlight"><pre><span></span><code><span id="__span-0-1"><a id="__codelineno-0-1" name="__codelineno-0-1" href="#__codelineno-0-1"></a><span class="nf">EthernetInterface</span><span class="p">(</span><span class="n">phy</span><span class="p">,</span> <span class="n">clk_freq</span><span class="p">,</span> <span class="n">fpga_ip_addr</span><span class="p">,</span> <span class="n">host_ip_addr</span><span class="p">,</span> <span class="n">udp_port</span><span class="o">=</span><span class="mi">2001</span><span class="p">,</span> <span class="o">**</span><span class="n">kwargs</span><span class="p">)</span>
|
||
</span></code></pre></div>
|
||
|
||
<div class="doc doc-contents first">
|
||
|
||
|
||
<p>A synthesizable module for Ethernet (UDP) communication between a host
|
||
machine and the FPGA.</p>
|
||
|
||
<p>This function is the main mechanism for configuring an Ethernet
|
||
Interface in an Amaranth-native design.</p>
|
||
|
||
|
||
<p><span class="doc-section-title">Parameters:</span></p>
|
||
<ul>
|
||
<li class="doc-section-item field-body">
|
||
<b><code>phy</code></b>
|
||
(<code>str</code>)
|
||
–
|
||
<div class="doc-md-description">
|
||
<p>The name of the LiteEth PHY class to use. Select the
|
||
appropriate one from <a href="https://github.com/enjoy-digital/liteeth/blob/main/liteeth/phy/__init__.py#L25-L45">this list</a>
|
||
for your FPGA vendor and family.</p>
|
||
</div>
|
||
</li>
|
||
<li class="doc-section-item field-body">
|
||
<b><code>clk_freq</code></b>
|
||
(<code>int | float</code>)
|
||
–
|
||
<div class="doc-md-description">
|
||
<p>The frequency of the clock provided to the
|
||
Manta module on the FPGA, in Hertz (Hz).</p>
|
||
</div>
|
||
</li>
|
||
<li class="doc-section-item field-body">
|
||
<b><code>fpga_ip_addr</code></b>
|
||
(<code>str</code>)
|
||
–
|
||
<div class="doc-md-description">
|
||
<p>The IP address the FPGA will attempt to claim.
|
||
Upon power-on, the FPGA will issue a DHCP request for this IP
|
||
address. Ping this address after power-on to check if this
|
||
request was successful, or check your router for a list of
|
||
connected devices.</p>
|
||
</div>
|
||
</li>
|
||
<li class="doc-section-item field-body">
|
||
<b><code>host_ip_addr</code></b>
|
||
(<code>str</code>)
|
||
–
|
||
<div class="doc-md-description">
|
||
<p>The IP address of the host machine, which the
|
||
FPGA will send packets back to.</p>
|
||
</div>
|
||
</li>
|
||
<li class="doc-section-item field-body">
|
||
<b><code>udp_port</code></b>
|
||
(<code>Optional[int]</code>, default:
|
||
<code>2001</code>
|
||
)
|
||
–
|
||
<div class="doc-md-description">
|
||
<p>The UDP port to communicate over.</p>
|
||
</div>
|
||
</li>
|
||
<li class="doc-section-item field-body">
|
||
<b><code>**kwargs</code></b>
|
||
–
|
||
<div class="doc-md-description">
|
||
<p>Any additional keyword arguments to this function will
|
||
be passed to the LiteEth RTL generator. Some examples are
|
||
provided below:</p>
|
||
<ul>
|
||
<li>
|
||
<p>mac_address (int): A 48-bit integer representing the MAC
|
||
address the FPGA will assume. If not provided, an address
|
||
within the <a href="https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses">Locally Administered, Administratively Assigned group</a>
|
||
will be randomly generated.</p>
|
||
</li>
|
||
<li>
|
||
<p>vendor (str): The vendor of your FPGA. Currently only values
|
||
of <code>xilinx</code> and <code>lattice</code> are supported. This is used to
|
||
generate (currently unused) timing constraints files.</p>
|
||
</li>
|
||
<li>
|
||
<p>toolchain (str): The toolchain being used. Currently only
|
||
values of <code>vivado</code> and <code>diamond</code> are supported.</p>
|
||
</li>
|
||
<li>
|
||
<p>refclk_freq (int | float): The frequency of the reference
|
||
clock to be provided to the Ethernet PHY, in Hertz (Hz).
|
||
This frequency must match the MII variant used by the PHY,
|
||
and speed it is being operated at. For instance, a RGMII
|
||
PHY may be operated at either 125MHz in Gigabit mode, or
|
||
25MHz in 100Mbps mode.</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
<div class="doc doc-children">
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
</div>
|
||
|
||
</div>
|
||
|
||
</div>
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
||
|
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