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<h2 id="system-architecture">System Architecture</h2>
<p>The whole system looks like the following:</p>
<p><center><img src="../assets/system_architecture.drawio.svg"></center></p>
<p>Manta consists of two parts - a Python API running on a host machine, and an autogenerated block of RTL that's included with your logic on a FPGA. Either UART or Ethernet is used for communication, which allows the host machine to operate the debugging cores on the FPGA.</p>
<h2 id="manta-architecture">Manta Architecture</h2>
<p>The logic Manta places on the FPGA consists of a series of cores connected in a chain along a common bus. Each core provides a unique method for interacting with the user’s logic, which it connects to by routing signals (called <em>probes</em>) between the user’s logic and the cores that interface with it.</p>
<p><center><img src="../assets/bus_architecture.drawio.svg"></center></p>
<p>These probes are presented as addressable memory, and are be controlled by reading and writing to their corresponding memory - not unlike registers on a microcontroller. Each core is allotted a section of address space at compile time, and operations addressed to a core’s address space control the behavior of the core. These cores are then daisy-chained along an internal bus, which permits a chain arbitrarily many cores to be placed on the bus.</p>
<p>At the beginning of this chain is a module called a <em>receive bridge</em>, which converts incoming UART/Ethernet communication from the host into read and write requests, which are placed on the bus. These are called <em>bus transactions</em>, and once placed on the bus, they travel through each core before reaching the <em>transmit bridge</em> at the end of the chain. This module places the result of the bus transaction back on the UART/Ethernet interface, and sends it back to the host. This produces a request-response style of communication between the host machine and the FPGA.</p>
<h2 id="data-bus">Data Bus</h2>
<p>The data bus is designed for simplicity, and consists of five signals used to perform reads and writes on memory:</p>
<ul>
<li><code>addr [15:0]</code>, indicating the memory address targeted by the current transaction.</li>
<li><code>data [15:0]</code>, which data is read from during a read, or written to during a write.</li>
<li><code>rw</code>, indicating a read or write transaction if the signal is low or high respectively.</li>
<li><code>valid</code>, which is driven high only when the operation specified by the other signals is to be executed.</li>
</ul>
<p>Each core has a bus input and output port, so that cores can be daisy-chained together. When it receives an incoming bus transaction (signalled by <code>valid</code>), the core checks the address on the wire against its own memory space. If the address lies within the core, the core will perform the requested operation against its own memory space. In the case of a read, it places the data at that address on <code>data</code>, and in the case of a write, it copies the value of <code>data</code> to the specified location in memory. However, if the address lies outside of the memory of the core, then no operations are performed.</p>
<style>
.svg-container {
background-color: white;
display: inline-block;
width: 49%;
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<p><img alt="Read Transaction" class="svg-container" src="https://svg.wavedrom.com/github/fischermoseley/manta/main/doc/assets/read_transaction.json5" />
<img alt="Write Transaction" class="svg-container" src="https://svg.wavedrom.com/github/fischermoseley/manta/main/doc/assets/write_transaction.json5" /></p>
<h2 id="message-format">Message Format</h2>
<p>Ethernet and UART both allow a stream of bytes to be sent between the host and FPGA, but since they're just interfaces, they don't define how these bytes are structured. As a result, Manta implements its own messaging format, with the following structure:</p>
<p><center><img src="../assets/uart_packets.drawio.svg"></center></p>
<p>Each of these messages is a string of ASCII characters consisting of a preamble, optional address and data fields, and an End of Line (EOL). The preamble denotes the type of operation, <em>R</em> for a read and <em>W</em> for a write. The address and data fields are encoded as hexadecimal digits, represented with the characters 0-9 and A-F in ASCII. As a result, four characters are needed to encode a 16-bit address or 16-bits of data. If the message specifies a write request, then it will contain a data field after the address field. Both request types will conclude with an End of Line, which consists of the two ASCII characters indicating a Carriage Return (CR) and a Line Feed (LF).</p>
<p>These requests are sent by the host machine to the FPGA, which reads them from the <code>rx</code> line on the interface transceiver. This is handled by the receive bridge, which parses incoming messages, and generates bus transactions from them. Once this transaction runs through every core in the chain, it arrives at the transmit bridge, which may send a response back to the host over the <code>tx</code> line.</p>
<p>If the request specified a read operation, then a response will be produced. These responses have the same structure as the read request itself, albeit with the data read from memory substituted in place of the address. This results in a message of the same length, just with the address swapped for data. If the request specified a write operation, then no response will be sent back to the host. Manta provides no report of if the write was successful - if a write operation must be verified, Manta will just perform a read operation on the same address location and check the value.</p>
<p>An example of some bus traffic is provided below:</p>
<table>
<thead>
<tr>
<th>Sequence Number</th>
<th>Interface Activity</th>
<th>Operation</th>
</tr>
</thead>
<tbody>
<tr>
<td>1</td>
<td>Host → FPGA: R1234(CR)(LF)</td>
<td>-</td>
</tr>
<tr>
<td>2</td>
<td>FPGA → Host: R5678(CR)(LF)</td>
<td>Read 0x5678 from 0x1234</td>
</tr>
<tr>
<td>3</td>
<td>Host → FPGA: WF00DBEEF(CR)(LF)</td>
<td>Write 0xBEEF to 0xF00D</td>
</tr>
<tr>
<td>4</td>
<td>Host → FPGA: RF00D(CR)(LF)</td>
<td>-</td>
</tr>
<tr>
<td>5</td>
<td>FPGA → Host: RBEEF(CR)(LF)</td>
<td>Read 0xBEEF from 0xF00D</td>
</tr>
<tr>
<td>6</td>
<td>Host → FPGA: W12340000(CR)(LF)</td>
<td>Write 0x0000 to 0x1234</td>
</tr>
</tbody>
</table>
<p>When UART is used, these bytes are transmitted directly across the wire, but when Ethernet is used, they're packed into the packet's payload field.</p>
<h1 id="cores">Cores</h1>
<h2 id="io-core">IO Core</h2>
<p>This is done with the architecture shown below:</p>
<p><center><img src="../assets/io_core_architecture.drawio.svg" width="60%"></center></p>
<p>Each of the probes is mapped to a register of Manta's internal memory. Since Manta's internal registers are 16 bits wide, probes less than 16 bits are mapped to a single register, but probes wider than 16 bits require multiple.</p>
<p>Whatever the number of registers required, these are read from and written to by the host machine - but the connection to the user's logic isn't direct. The value of each probe is buffered, and only once the <code>strobe</code> register has been set to one will the buffers update. When this happens, output probes provide new values to user logic, and new values for input probes are read from user logic. This provides a convenient place to perform clock domain crossing, and also mitigates the possibility of an inconsistent system state. This is explained in more detail in Chapter 3.6 of the <a href="../thesis.pdf">original thesis</a>.</p>
<h2 id="logic-analyzer">Logic Analyzer</h2>
<p>The Logic Analyzer Core's implementation on the FPGA consists of three primary components:</p>
<p><center><img src="../assets/logic_analyzer_architecture.drawio.svg" width="85%"></center></p>
<ul>
<li>The <em>Finite State Machine (FSM)</em>, which controls the operation of the core. The FSM's operation is driven by its associated registers, which are placed in a separate module. This permits simple CDC between the bus and user clock domains.</li>
<li>The <em>Trigger Block</em>, which generates the core's trigger condition. The trigger block contains a trigger for each input probe, and the registers necessary to configure them. It also contains the <span class="arithmatex">\(N\)</span>-logic gate (either AND or OR) that generates the core's trigger from the individual probe triggers. CDC is performed in exactly the same manner as the FSM. If an external trigger is specified, the trigger block is omitted from the Logic Analyzer Core, and the external trigger is routed to the FSM's <code>trig</code> input.</li>
<li>The <em>Sample Memory</em>, which stores the states of the probes during a capture. This is implemented as a dual-port, dual-clock block memory, with the bus on one port and the probes on the other. The probe-connected port only writes to the memory, with the address and enable pins managed by the FSM. CDC is performed in the block RAM primitive itself.</li>
</ul>
<h2 id="memory-core">Memory Core</h2>
<p>Each Memory core is actually a set of 16-bit wide BRAMs with their ports concatenated together, with any spare bits masked off. Here's a diagram:</p>
<p><center><img src="../assets/memory_architecture.drawio.svg" width="85%"></center></p>
<p>Since each <span class="arithmatex">\(n\)</span>-bit wide block memory is actually <span class="arithmatex">\(ceil(n/16)\)</span> BRAMs under the hood, addressing the BRAMs correctly from Manta's internal bus is important. BRAMs are organized such that each 16-bit slice of a <span class="arithmatex">\(N\)</span>-bit word in the Block Memory core are placed next to each other in bus address space. For instance, a 34-bit wide block memory would exist on Manta's internal bus as:</p>
<table>
<thead>
<tr>
<th>Bus Address Space</th>
<th>BRAM Address Space</th>
</tr>
</thead>
<tbody>
<tr>
<td>BASE_ADDR + 0</td>
<td>address 0, bits 0-15</td>
</tr>
<tr>
<td>BASE_ADDR + 1</td>
<td>address 1, bits 0-15</td>
</tr>
<tr>
<td>BASE_ADDR + n</td>
<td>address n, bits 0-15</td>
</tr>
<tr>
<td>...</td>
<td>...</td>
</tr>
<tr>
<td>BASE_ADDR + 0 + DEPTH</td>
<td>address 0, bits 16-31</td>
</tr>
<tr>
<td>BASE_ADDR + 1 + DEPTH</td>
<td>address 1, bits 16-31</td>
</tr>
<tr>
<td>BASE_ADDR + n + DEPTH</td>
<td>address n, bits 16-31</td>
</tr>
<tr>
<td>...</td>
<td>...</td>
</tr>
<tr>
<td>BASE_ADDR + 0 + (2 * DEPTH)</td>
<td>address 0, bits 32-33</td>
</tr>
<tr>
<td>BASE_ADDR + 1 + (2 * DEPTH)</td>
<td>address 1, bits 32-33</td>
</tr>
<tr>
<td>BASE_ADDR + n + (2 * DEPTH)</td>
<td>address n, bits 32-33</td>
</tr>
<tr>
<td>...</td>
<td>...</td>
</tr>
</tbody>
</table>
<p>...and so on.</p>
</article>
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