46 lines
968 B
Systemverilog
46 lines
968 B
Systemverilog
`default_nettype none
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`timescale 1ns / 1ps
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module top_level (
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input wire clk,
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input wire btnc,
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output logic [15:0] led,
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output logic ca, cb, cc, cd, ce, cf, cg,
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output logic dp,
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output logic [7:0] an,
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input wire uart_txd_in,
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output logic uart_rxd_out
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);
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manta manta_inst (
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.clk(clk),
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.rx(uart_txd_in),
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.tx(uart_rxd_out));
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// Show bus on 7-segment display
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reg [15:0] addr_latched = 0;
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reg [15:0] data_latched = 0;
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reg rw_latched = 0;
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always @(posedge clk) begin
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if (manta.brx_my_lut_mem_valid) begin
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addr_latched <= manta.my_lut_mem_brx_addr;
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data_latched <= manta.my_lut_mem_brx_data;
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rw_latched <= manta.my_lut_mem_btx_rw;
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end
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end
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ssd ssd (
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.clk(clk),
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.val( (addr_latched << 16) | (data_latched) ),
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.cat({cg,cf,ce,cd,cc,cb,ca}),
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.an(an));
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assign dp = rw_latched;
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endmodule
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`default_nettype wire |