112 lines
3.4 KiB
Python
112 lines
3.4 KiB
Python
from amaranth import *
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from cobs import cobs
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from manta import *
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from manta.ethernet.bridge import EthernetBridge
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from manta.uart.cobs_decode import COBSDecode
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from manta.uart.cobs_encode import COBSEncode
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from manta.uart.receiver import UARTReceiver
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from manta.uart.stream_packer import StreamPacker
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from manta.uart.stream_unpacker import StreamUnpacker
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from manta.uart.transmitter import UARTTransmitter
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from manta.utils import *
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# uart_rx -> COBS decode -> pack_stream -> bridge -> unpack_stream -> COBS encode -> uart_tx
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class UARTHardware(Elaboratable):
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def __init__(self):
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self.rx = Signal()
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self.tx = Signal()
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self.bus_o = Signal(InternalBus())
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self.bus_i = Signal(InternalBus())
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self._clocks_per_baud = 10
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def elaborate(self, platform):
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m = Module()
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m.submodules.uart_rx = uart_rx = UARTReceiver(self._clocks_per_baud)
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m.submodules.cobs_decode = cobs_decode = COBSDecode()
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m.submodules.stream_packer = stream_packer = StreamPacker()
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m.submodules.bridge = bridge = EthernetBridge()
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m.submodules.stream_unpacker = stream_unpacker = StreamUnpacker()
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m.submodules.cobs_encode = cobs_encode = COBSEncode()
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m.submodules.uart_tx = uart_tx = UARTTransmitter(self._clocks_per_baud)
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wiring.connect(m, uart_rx.source, cobs_decode.sink)
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wiring.connect(m, cobs_decode.source, stream_packer.sink)
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wiring.connect(m, stream_packer.source, bridge.sink)
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wiring.connect(m, bridge.source, stream_unpacker.sink)
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wiring.connect(m, stream_unpacker.source, cobs_encode.sink)
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wiring.connect(m, cobs_encode.source, uart_tx.sink)
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m.d.comb += [
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uart_rx.rx.eq(self.rx),
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self.tx.eq(uart_tx.tx),
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self.bus_o.eq(bridge.bus_o),
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bridge.bus_i.eq(self.bus_i),
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]
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return m
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class UARTHardwarePlusMemoryCore(Elaboratable):
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def __init__(self):
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self.rx = Signal()
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self.tx = Signal()
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self._clocks_per_baud = 10
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def elaborate(self, platform):
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m = Module()
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m.submodules.uart = uart = UARTHardware()
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m.submodules.mem_core = mem_core = MemoryCore("bidirectional", 32, 1024)
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mem_core.base_addr = 0
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m.d.comb += uart.bus_i.eq(mem_core.bus_o)
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m.d.comb += mem_core.bus_i.eq(uart.bus_o)
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m.d.comb += [
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self.tx.eq(uart.tx),
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uart.rx.eq(self.rx),
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]
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return m
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uart_hw = UARTHardwarePlusMemoryCore()
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async def send_byte(ctx, module, data):
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# 8N1 serial, LSB sent first
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data_bits = "0" + f"{data:08b}"[::-1] + "1"
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data_bits = [int(bit) for bit in data_bits]
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for i in range(10 * uart_hw._clocks_per_baud):
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bit_index = i // uart_hw._clocks_per_baud
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ctx.set(module.rx, data_bits[bit_index])
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await ctx.tick()
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@simulate(uart_hw)
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async def test_read_request(ctx):
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addr = 0x5678_9ABC
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header = EthernetMessageHeader.from_params(
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MessageTypes.READ_REQUEST, seq_num=0x0, length=1
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)
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request = bytestring_from_ints([header.as_bits(), addr], byteorder="little")
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encoded = cobs.encode(request)
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encoded = encoded + int(0).to_bytes(1)
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ctx.set(uart_hw.rx, 1)
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await ctx.tick()
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await ctx.tick()
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await ctx.tick()
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for byte in encoded:
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await send_byte(ctx, uart_hw, int(byte))
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print(hex(int(byte)))
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await ctx.tick()
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