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manta/examples/verilog/nexys_a7/logic_analyzer_uart
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Fischer Moseley 04cfa41190 add logic analyzer/io core ethernet example 2024-03-07 09:18:30 -08:00
..
.gitignore add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00
build.sh add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00
build.tcl add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00
manta.yaml add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00
top_level.sv add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00
top_level.xdc add examples for the Nexys4DDR, bump version to 1.0.0 2024-03-06 23:07:20 -08:00