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test_bridge_rx_sim.py
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meta: sort imports with ruff
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2024-09-14 10:23:05 -07:00 |
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test_bridge_tx_sim.py
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meta: sort imports with ruff
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2024-09-14 10:23:05 -07:00 |
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test_config_export.py
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tests: fix test_config_export
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2024-09-14 12:53:17 -07:00 |
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test_examples_build.py
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meta: sort imports with ruff
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2024-09-14 10:23:05 -07:00 |
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test_interfaces_e2e_sim.py
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uart: begin bringing up COBS
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2024-10-06 09:20:27 -06:00 |
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test_io_core_hw.py
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docs: autogenerate Python API docs, update IO core docs
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2024-09-14 10:23:05 -07:00 |
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test_io_core_sim.py
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docs: autogenerate Python API docs, update IO core docs
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2024-09-14 10:23:05 -07:00 |
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test_logic_analyzer_fsm_sim.py
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tests: refactor to use Amaranth-native API
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2024-09-14 10:22:32 -07:00 |
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test_logic_analyzer_hw.py
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docs: autogenerate Python API docs, update IO core docs
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2024-09-14 10:23:05 -07:00 |
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test_logic_analyzer_sim.py
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docs: autogenerate Python API docs, update IO core docs
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2024-09-14 10:23:05 -07:00 |
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test_mem_core_hw.py
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docs: autogenerate Python API docs, update IO core docs
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2024-09-14 10:23:05 -07:00 |
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test_mem_core_sim.py
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docs: autogenerate Python API docs, update IO core docs
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2024-09-14 10:23:05 -07:00 |
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test_source_bridge_sim.py
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meta: sort imports with ruff
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2024-09-14 10:23:05 -07:00 |
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test_toolchains.py
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docs: autogenerate Python API docs, update IO core docs
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2024-09-14 10:23:05 -07:00 |
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test_uart_baud_mismatch.py
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uart: remove flaky nexys4ddr baudrate mismatch test case
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2024-09-22 18:45:06 -07:00 |
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test_uart_rx_sim.py
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meta: sort imports with ruff
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2024-09-14 10:23:05 -07:00 |
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test_uart_tx_sim.py
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meta: sort imports with ruff
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2024-09-14 10:23:05 -07:00 |
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test_verilog_gen.py
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meta: sort imports with ruff
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2024-09-14 10:23:05 -07:00 |
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test_verilog_gen.yaml
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inital source, imported from splat
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2023-12-28 14:22:29 -08:00 |
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