Commit Graph

9 Commits

Author SHA1 Message Date
Fischer Moseley aa2ba43e8f rename lut mem to lut ram, add to manta generator 2023-03-14 16:24:56 -04:00
Fischer Moseley 8630da53d8 hack manta source files together 2023-03-14 16:24:56 -04:00
Fischer Moseley f5f7f91bdc fix LogicAnalyzerCore instantiation from file 2023-03-14 16:24:56 -04:00
Fischer Moseley 334aa8c005 refactor __init__.py to be object-oriented 2023-03-14 16:24:56 -04:00
Fischer Moseley e022696b31 add working example for macOS bug 2023-03-14 16:24:56 -04:00
Fischer Moseley 70e2bd10e7 rename, slightly patch bridge_tx 2023-03-14 16:24:56 -04:00
Fischer Moseley 3124430064 tidy up a little, convert things to verilog 2023-03-14 16:24:56 -04:00
Fischer Moseley 3ff4298e24 works (kinda) on hardware 2023-03-14 16:24:56 -04:00
Fischer Moseley 3728a5263d
add icestick builds / iCE40 to CI (#1)
* initial commit

* fix yaml file

* add yosys deps to CI

* fix indentation in ice40 CI builds

* update ice40 CI

* try using oss cad suite instead of compiling from source

* fix pathing directory

* ensure jobs are sequential

* ensure we're in the same shell

* move source files to same action

* update icestick project structure to match the a7's

* update build script for ice40 to match updated proj structure

* update CI to match previous

* update CI path

* update build script naming

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Co-authored-by: fischerm <fischerm@EECS-DIGITAL-55.MIT.EDU>
2023-02-23 18:52:22 -05:00