Fischer Moseley
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25ebae42e2
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add GateMate ILA to alternatives
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2024-03-03 13:57:52 -08:00 |
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Fischer Moseley
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11022f474d
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refactor Memory Core simulation into test class
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2024-03-03 13:30:54 -08:00 |
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Fischer Moseley
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e2d52a6e2d
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add simulate decorator
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2024-03-03 02:14:12 -08:00 |
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Fischer Moseley
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2e2397013e
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make mem_core_hw tests pass
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2024-03-02 14:08:52 -08:00 |
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Fischer Moseley
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40a57651bb
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shorten methods in MemoryCore
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2024-03-02 13:44:08 -08:00 |
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Fischer Moseley
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6438a55192
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partially revert MemoryCore updates
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2024-03-02 13:31:01 -08:00 |
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Fischer Moseley
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6aea5cc6e1
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update MemoryCore references
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2024-03-02 12:52:04 -08:00 |
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Fischer Moseley
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ab7d9105b1
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add preliminary bidirectional memory core
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2024-02-28 10:36:27 -08:00 |
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Fischer Moseley
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8a2b9ced76
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add ethernet PHY IO autoassignment
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2024-02-19 17:19:23 -08:00 |
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Fischer Moseley
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491db38def
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tidy DHCP counter
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2024-02-19 13:53:04 -08:00 |
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Fischer Moseley
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ca7d743bf4
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move to private methods in Manta class
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2024-02-19 12:15:19 -08:00 |
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Fischer Moseley
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b0dcd269bc
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add from_config to memory_core
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2024-02-19 11:42:28 -08:00 |
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Fischer Moseley
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7ee51158d2
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enforce consistent docstrings and underscores in logic analyzer core
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2024-02-19 11:23:11 -08:00 |
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Fischer Moseley
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e2450ddbff
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complete IO core refactor
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2024-02-18 15:50:51 -08:00 |
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Fischer Moseley
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0c0f31be64
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rewrite IO Core
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2024-02-18 13:50:26 -08:00 |
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Fischer Moseley
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3f724b3336
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add width check function to utils
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2024-02-17 21:34:17 -08:00 |
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Fischer Moseley
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ea6b3f73b9
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add docstrings
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2024-02-17 16:07:29 -08:00 |
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Fischer Moseley
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0e1bc30802
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wrap docstrings at 80 chars
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2024-02-17 15:18:57 -08:00 |
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Fischer Moseley
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68aeb1a4a8
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add underscores for private objects
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2024-02-17 15:04:50 -08:00 |
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Fischer Moseley
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8aedb8e968
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add config check to ethernet interface
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2024-02-17 14:09:29 -08:00 |
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Fischer Moseley
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1487cfe9a2
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banish relative imports
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2024-02-17 13:31:27 -08:00 |
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Fischer Moseley
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a1fddf555e
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move init'ing UARTInterface from config to classmethod
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2024-02-12 08:50:43 -08:00 |
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Fischer Moseley
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75a0fe46ff
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fix PLL information in Ethernet docs
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2024-02-10 01:13:11 -08:00 |
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Fischer Moseley
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5e642101ef
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pass Ethernet config to LiteEth core generator
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2024-02-10 00:48:53 -08:00 |
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Fischer Moseley
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63e912fb63
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fix grammar and diagrams
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2024-02-09 22:49:58 -08:00 |
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Fischer Moseley
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24ee956d6c
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add liteeth wrapper
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2024-02-09 18:58:02 -08:00 |
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Fischer Moseley
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a5afad6992
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io core with ethernet working!
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2024-02-04 14:29:39 -08:00 |
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Fischer Moseley
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a75a6a3ccf
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add first pass at ethernet
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2024-01-28 21:54:46 -08:00 |
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Fischer Moseley
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510bae6f38
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add MATLAB fpga data capture to alternatives, thanks nathan
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2024-01-22 00:03:54 -08:00 |
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Fischer Moseley
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ee4a79a4d4
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refactor logic analyzer FSM to be sequential-only for better timing
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2024-01-21 23:45:14 -08:00 |
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Fischer Moseley
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c177e3b5b5
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update makefile to source venv again
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2024-01-21 00:50:53 -08:00 |
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Fischer Moseley
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d075c04e2a
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update makefile to not require python scripts on PATH
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2024-01-21 00:47:14 -08:00 |
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Fischer Moseley
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b8de6339aa
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adjust some ergonomics found while playtesting
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2024-01-21 00:23:07 -08:00 |
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Fischer Moseley
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ab0909d06b
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refactor logic analyzer to use enums, add incremental + immediate trigger modes
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2024-01-20 21:59:42 -08:00 |
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Fischer Moseley
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6e3fe8cb0e
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add initial FSM tests
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2024-01-20 15:25:04 -08:00 |
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Fischer Moseley
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a8b43849ec
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remove trig_blk test - was not adding value
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2024-01-15 12:33:59 -08:00 |
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Fischer Moseley
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edd00310c4
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first pass at logic analyzer trigger block tests
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2024-01-14 14:49:02 -08:00 |
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Fischer Moseley
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1528f569ef
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update submodule usage, tidy logic analyzer config check
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2024-01-14 12:51:52 -08:00 |
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Fischer Moseley
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970499d137
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remove ANSI escape codes, they don't work in command prompt
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2024-01-13 15:52:06 -08:00 |
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Fischer Moseley
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2b95fea496
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update docs, bump required python to 3.8
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2024-01-13 15:05:45 -08:00 |
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Fischer Moseley
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4e44f7ac90
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add version command to CLI
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2024-01-11 10:40:12 -08:00 |
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Fischer Moseley
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c1c0330d86
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fix bug in USB PID/VID reporting
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2024-01-11 09:33:21 -08:00 |
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Fischer Moseley
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487b11f155
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complete refactor to InternalBus()
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2024-01-07 22:35:15 -08:00 |
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Fischer Moseley
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a7625ce0a4
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refactor uart into multiple files
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2024-01-07 21:54:14 -08:00 |
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Fischer Moseley
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7a6ab45b92
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revert UART and InternalBus() refactor
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2024-01-07 21:39:44 -08:00 |
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Fischer Moseley
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fbaf93b110
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fix typo introduced during refactor
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2024-01-07 18:54:33 -08:00 |
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Fischer Moseley
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ee4a3026af
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refactor to use common bus layout across all modules
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2024-01-07 18:17:09 -08:00 |
fischerm
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61d6479805
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add docstrings
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2024-01-07 15:13:35 -08:00 |
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Fischer Moseley
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4c48035201
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track amaranth release, not main repo
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2024-01-07 12:49:20 -08:00 |
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fischerm
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7fc7ddc75c
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fix bad comb assignment
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2024-01-07 12:09:38 -08:00 |