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UART Interface
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Ethernet Interface
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@ -874,7 +998,9 @@
<li class="md-nav__item">
<a href="#memory-core" class="md-nav__link">
<span class="md-ellipsis">
Memory Core
Memory Core
</span>
</a>
@ -895,6 +1021,7 @@
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@ -906,11 +1033,13 @@
<h2 id="system-architecture">System Architecture</h2>
<p>The whole system looks like the following:</p>
<p><center><img src="../assets/system_architecture.drawio.svg"></center></p>
<center><img src="../assets/system_architecture.drawio.svg"></center>
<p>Manta consists of two parts - a Python API running on a host machine, and an autogenerated block of RTL that's included with your logic on a FPGA. Either UART or Ethernet is used for communication, which allows the host machine to operate the debugging cores on the FPGA.</p>
<h2 id="manta-architecture">Manta Architecture</h2>
<p>The logic Manta places on the FPGA consists of a series of cores connected in a chain along a common bus. Each core provides a unique method for interacting with the users logic, which it connects to by routing signals (called <em>probes</em>) between the users logic and the cores that interface with it.</p>
<p><center><img src="../assets/bus_architecture.drawio.svg"></center></p>
<center><img src="../assets/bus_architecture.drawio.svg"></center>
<p>These probes are presented as addressable memory, and are be controlled by reading and writing to their corresponding memory - not unlike registers on a microcontroller. Each core is allotted a section of address space at compile time, and operations addressed to a cores address space control the behavior of the core. These cores are then daisy-chained along an internal bus, which permits a chain arbitrarily many cores to be placed on the bus.</p>
<p>At the beginning of this chain is a module called a <em>receive bridge</em>, which converts incoming UART/Ethernet communication from the host into read and write requests, which are placed on the bus. These are called <em>bus transactions</em>, and once placed on the bus, they travel through each core before reaching the <em>transmit bridge</em> at the end of the chain. This module places the result of the bus transaction back on the UART/Ethernet interface, and sends it back to the host. This produces a request-response style of communication between the host machine and the FPGA.</p>
<h2 id="data-bus">Data Bus</h2>
@ -934,7 +1063,8 @@
<img alt="Write Transaction" class="svg-container" src="https://svg.wavedrom.com/github/fischermoseley/manta/main/doc/assets/write_transaction.json5" /></p>
<h2 id="message-format">Message Format</h2>
<p>Ethernet and UART both allow a stream of bytes to be sent between the host and FPGA, but since they're just interfaces, they don't define how these bytes are structured. As a result, Manta implements its own messaging format, with the following structure:</p>
<p><center><img src="../assets/uart_packets.drawio.svg"></center></p>
<center><img src="../assets/uart_packets.drawio.svg"></center>
<p>Each of these messages is a string of ASCII characters consisting of a preamble, optional address and data fields, and an End of Line (EOL). The preamble denotes the type of operation, <em>R</em> for a read and <em>W</em> for a write. The address and data fields are encoded as hexadecimal digits, represented with the characters 0-9 and A-F in ASCII. As a result, four characters are needed to encode a 16-bit address or 16-bits of data. If the message specifies a write request, then it will contain a data field after the address field. Both request types will conclude with an End of Line, which consists of the two ASCII characters indicating a Carriage Return (CR) and a Line Feed (LF).</p>
<p>These requests are sent by the host machine to the FPGA, which reads them from the <code>rx</code> line on the interface transceiver. This is handled by the receive bridge, which parses incoming messages, and generates bus transactions from them. Once this transaction runs through every core in the chain, it arrives at the transmit bridge, which may send a response back to the host over the <code>tx</code> line.</p>
<p>If the request specified a read operation, then a response will be produced. These responses have the same structure as the read request itself, albeit with the data read from memory substituted in place of the address. This results in a message of the same length, just with the address swapped for data. If the request specified a write operation, then no response will be sent back to the host. Manta provides no report of if the write was successful - if a write operation must be verified, Manta will just perform a read operation on the same address location and check the value.</p>
@ -984,12 +1114,14 @@
<h1 id="cores">Cores</h1>
<h2 id="io-core">IO Core</h2>
<p>This is done with the architecture shown below:</p>
<p><center><img src="../assets/io_core_architecture.drawio.svg" width="60%"></center></p>
<center><img src="../assets/io_core_architecture.drawio.svg" width="60%"></center>
<p>Each of the probes is mapped to a register of Manta's internal memory. Since Manta's internal registers are 16 bits wide, probes less than 16 bits are mapped to a single register, but probes wider than 16 bits require multiple.</p>
<p>Whatever the number of registers required, these are read from and written to by the host machine - but the connection to the user's logic isn't direct. The value of each probe is buffered, and only once the <code>strobe</code> register has been set to one will the buffers update. When this happens, output probes provide new values to user logic, and new values for input probes are read from user logic. This provides a convenient place to perform clock domain crossing, and also mitigates the possibility of an inconsistent system state. This is explained in more detail in Chapter 3.6 of the <a href="../thesis.pdf">original thesis</a>.</p>
<h2 id="logic-analyzer">Logic Analyzer</h2>
<p>The Logic Analyzer Core's implementation on the FPGA consists of three primary components:</p>
<p><center><img src="../assets/logic_analyzer_architecture.drawio.svg" width="85%"></center></p>
<center><img src="../assets/logic_analyzer_architecture.drawio.svg" width="85%"></center>
<ul>
<li>The <em>Finite State Machine (FSM)</em>, which controls the operation of the core. The FSM's operation is driven by its associated registers, which are placed in a separate module. This permits simple CDC between the bus and user clock domains.</li>
<li>The <em>Trigger Block</em>, which generates the core's trigger condition. The trigger block contains a trigger for each input probe, and the registers necessary to configure them. It also contains the <span class="arithmatex">\(N\)</span>-logic gate (either AND or OR) that generates the core's trigger from the individual probe triggers. CDC is performed in exactly the same manner as the FSM. If an external trigger is specified, the trigger block is omitted from the Logic Analyzer Core, and the external trigger is routed to the FSM's <code>trig</code> input.</li>
@ -997,7 +1129,8 @@
</ul>
<h2 id="memory-core">Memory Core</h2>
<p>Each Memory core is actually a set of 16-bit wide BRAMs with their ports concatenated together, with any spare bits masked off. Here's a diagram:</p>
<p><center><img src="../assets/memory_architecture.drawio.svg" width="85%"></center></p>
<center><img src="../assets/memory_architecture.drawio.svg" width="85%"></center>
<p>Since each <span class="arithmatex">\(n\)</span>-bit wide block memory is actually <span class="arithmatex">\(ceil(n/16)\)</span> BRAMs under the hood, addressing the BRAMs correctly from Manta's internal bus is important. BRAMs are organized such that each 16-bit slice of a <span class="arithmatex">\(N\)</span>-bit word in the Block Memory core are placed next to each other in bus address space. For instance, a 34-bit wide block memory would exist on Manta's internal bus as:</p>
<table>
<thead>
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@ -19,8 +19,11 @@
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fischermoseley/manta
@ -251,10 +253,15 @@
<span class="md-ellipsis">
Home
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@ -273,10 +280,15 @@
<span class="md-ellipsis">
Installation
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@ -295,10 +307,15 @@
<span class="md-ellipsis">
Getting Started
</span>
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@ -317,10 +334,15 @@
<span class="md-ellipsis">
Use Cases
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</a>
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@ -339,10 +361,15 @@
<span class="md-ellipsis">
Architecture
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@ -361,10 +388,15 @@
<span class="md-ellipsis">
Similar Tools
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@ -401,10 +433,15 @@
<span class="md-ellipsis">
Cores
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<span class="md-nav__icon md-icon"></span>
</label>
@ -412,7 +449,11 @@
<nav class="md-nav" data-md-level="1" aria-labelledby="__nav_7_label" aria-expanded="false">
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<span class="md-nav__icon md-icon"></span>
Cores
Cores
</label>
<ul class="md-nav__list" data-md-scrollfix>
@ -428,10 +469,15 @@
<span class="md-ellipsis">
IO Core
</span>
</a>
</li>
@ -451,10 +497,15 @@
<span class="md-ellipsis">
Logic Analyzer Core
</span>
</a>
</li>
@ -474,10 +525,15 @@
<span class="md-ellipsis">
Memory Core
</span>
</a>
</li>
@ -522,10 +578,15 @@
<span class="md-ellipsis">
Interfaces
</span>
<span class="md-nav__icon md-icon"></span>
</label>
@ -533,7 +594,11 @@
<nav class="md-nav" data-md-level="1" aria-labelledby="__nav_8_label" aria-expanded="true">
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<span class="md-nav__icon md-icon"></span>
Interfaces
Interfaces
</label>
<ul class="md-nav__list" data-md-scrollfix>
@ -549,10 +614,15 @@
<span class="md-ellipsis">
UART Interface
</span>
</a>
</li>
@ -579,10 +649,15 @@
<span class="md-ellipsis">
Ethernet Interface
</span>
<span class="md-nav__icon md-icon"></span>
</label>
@ -592,10 +667,15 @@
<span class="md-ellipsis">
Ethernet Interface
</span>
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@ -615,7 +695,9 @@
<li class="md-nav__item">
<a href="#overview" class="md-nav__link">
<span class="md-ellipsis">
Overview
Overview
</span>
</a>
@ -624,7 +706,9 @@
<li class="md-nav__item">
<a href="#configuration" class="md-nav__link">
<span class="md-ellipsis">
Configuration
Configuration
</span>
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@ -634,7 +718,9 @@
<li class="md-nav__item">
<a href="#verilog-based-workflows" class="md-nav__link">
<span class="md-ellipsis">
Verilog-Based Workflows
Verilog-Based Workflows
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@ -643,7 +729,9 @@
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<span class="md-ellipsis">
Amaranth-Native Designs
Amaranth-Native Designs
</span>
</a>
@ -652,7 +740,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;EthernetInterface
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;EthernetInterface
</span>
</a>
@ -662,7 +752,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_mii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_mii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_mii_phy_io
</span>
</a>
@ -671,7 +763,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_rmii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_rmii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_rmii_phy_io
</span>
</a>
@ -680,7 +774,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_gmii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_gmii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_gmii_phy_io
</span>
</a>
@ -689,7 +785,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_rgmii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_rgmii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_rgmii_phy_io
</span>
</a>
@ -698,7 +796,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_sgmii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_sgmii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_sgmii_phy_io
</span>
</a>
@ -760,10 +860,15 @@
<span class="md-ellipsis">
For Developers
</span>
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</label>
@ -771,7 +876,11 @@
<nav class="md-nav" data-md-level="1" aria-labelledby="__nav_9_label" aria-expanded="false">
<label class="md-nav__title" for="__nav_9">
<span class="md-nav__icon md-icon"></span>
For Developers
For Developers
</label>
<ul class="md-nav__list" data-md-scrollfix>
@ -787,10 +896,15 @@
<span class="md-ellipsis">
Roadmap
</span>
</a>
</li>
@ -832,7 +946,9 @@
<li class="md-nav__item">
<a href="#overview" class="md-nav__link">
<span class="md-ellipsis">
Overview
Overview
</span>
</a>
@ -841,7 +957,9 @@
<li class="md-nav__item">
<a href="#configuration" class="md-nav__link">
<span class="md-ellipsis">
Configuration
Configuration
</span>
</a>
@ -851,7 +969,9 @@
<li class="md-nav__item">
<a href="#verilog-based-workflows" class="md-nav__link">
<span class="md-ellipsis">
Verilog-Based Workflows
Verilog-Based Workflows
</span>
</a>
@ -860,7 +980,9 @@
<li class="md-nav__item">
<a href="#amaranth-native-designs" class="md-nav__link">
<span class="md-ellipsis">
Amaranth-Native Designs
Amaranth-Native Designs
</span>
</a>
@ -869,7 +991,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;EthernetInterface
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;EthernetInterface
</span>
</a>
@ -879,7 +1003,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_mii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_mii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_mii_phy_io
</span>
</a>
@ -888,7 +1014,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_rmii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_rmii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_rmii_phy_io
</span>
</a>
@ -897,7 +1025,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_gmii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_gmii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_gmii_phy_io
</span>
</a>
@ -906,7 +1036,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_rgmii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_rgmii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_rgmii_phy_io
</span>
</a>
@ -915,7 +1047,9 @@
<li class="md-nav__item">
<a href="#manta.EthernetInterface.set_sgmii_phy_io" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_sgmii_phy_io
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_sgmii_phy_io
</span>
</a>
@ -941,6 +1075,7 @@
<div class="md-content" data-md-component="content">
<article class="md-content__inner md-typeset">
@ -1036,6 +1171,7 @@ Inside this configuration, the following parameters may be set:</p>
<div class="doc doc-contents first">
<p>A synthesizable module for Ethernet (UDP) communication between a host
machine and the FPGA.</p>
@ -1140,7 +1276,9 @@ provided below:</p>
<div class="doc doc-children">
<div class="doc doc-children">
@ -1808,10 +1946,11 @@ design.</p>
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Adding Manta as an Instance Variable
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Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping
Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping
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Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping
Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping
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Logic Analyzer Core
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<p>The latest development snapshot of Manta can be installed with:</p>
<div class="language-bash highlight"><pre><span></span><code><span id="__span-2-1"><a id="__codelineno-2-1" name="__codelineno-2-1" href="#__codelineno-2-1"></a>pip<span class="w"> </span>install<span class="w"> </span>--upgrade<span class="w"> </span>git+https://github.com/fischermoseley/manta.git
</span></code></pre></div>
<p>It's recommended to install Manta into a virtual environment, instead of your system Python. Among the many other benefits virtual environments offer, this will conveniently add the <code>manta</code> executable to your PATH. This allows you to invoke the tool with <code>manta</code>, rather than the more verbose <code>python3 -m manta</code>.</p>
<h2 id="editable-development-install">Editable Development Install</h2>
<p>If you're working on the source, you might want an editable installation with some extra dependencies used for development:</p>
<div class="language-bash highlight"><pre><span></span><code><span id="__span-3-1"><a id="__codelineno-3-1" name="__codelineno-3-1" href="#__codelineno-3-1"></a>git<span class="w"> </span>clone<span class="w"> </span>https://github.com/fischermoseley/manta.git
</span><span id="__span-3-2"><a id="__codelineno-3-2" name="__codelineno-3-2" href="#__codelineno-3-2"></a><span class="nb">cd</span><span class="w"> </span>manta
</span><span id="__span-3-3"><a id="__codelineno-3-3" name="__codelineno-3-3" href="#__codelineno-3-3"></a>pip<span class="w"> </span>install<span class="w"> </span>-e<span class="w"> </span><span class="s2">&quot;.[dev]&quot;</span>
</span><span id="__span-3-4"><a id="__codelineno-3-4" name="__codelineno-3-4" href="#__codelineno-3-4"></a>pre-commit<span class="w"> </span>install
</span></code></pre></div>
<p>Manta's hardware-in-the-loop tests rely on Amaranth's build system for programming FPGAs, which in turn relies on the <code>amaranth-boards</code> Python package. This package is not available on PyPI, and must be installed manually with:</p>
<div class="language-bash highlight"><pre><span></span><code><span id="__span-4-1"><a id="__codelineno-4-1" name="__codelineno-4-1" href="#__codelineno-4-1"></a>pip<span class="w"> </span>install<span class="w"> </span>git+https://github.com/amaranth-lang/amaranth-boards.git
</span><span id="__span-3-3"><a id="__codelineno-3-3" name="__codelineno-3-3" href="#__codelineno-3-3"></a>uv<span class="w"> </span>sync
</span><span id="__span-3-4"><a id="__codelineno-3-4" name="__codelineno-3-4" href="#__codelineno-3-4"></a><span class="nb">source</span><span class="w"> </span>.venv/bin/activate
</span><span id="__span-3-5"><a id="__codelineno-3-5" name="__codelineno-3-5" href="#__codelineno-3-5"></a>pre-commit<span class="w"> </span>install
</span></code></pre></div>
<p>The build system also uses the open-source <code>xc3sprog</code> and <code>iceprog</code> tools for programming Xilinx and ice40 devices, respectively. If you'd like to run these tests locally, you may need to install these tools and have them available on your <code>PATH</code>.</p>
<p>If you're on Linux, you may also need to add a new udev rule to give non-superuser accounts access to any connected FTDI devices. This can be done by making a new file at <code>/etc/udev/rules.d/99-ftdi-devices.rules</code>, which contains:</p>
<div class="language-text highlight"><pre><span></span><code><span id="__span-5-1"><a id="__codelineno-5-1" name="__codelineno-5-1" href="#__codelineno-5-1"></a>ACTION==&quot;add&quot;, ATTR{idVendor}==&quot;0403&quot;, ATTR{idProduct}==&quot;6010&quot;, MODE:=&quot;666&quot;
<div class="language-text highlight"><pre><span></span><code><span id="__span-4-1"><a id="__codelineno-4-1" name="__codelineno-4-1" href="#__codelineno-4-1"></a>ACTION==&quot;add&quot;, ATTR{idVendor}==&quot;0403&quot;, ATTR{idProduct}==&quot;6010&quot;, MODE:=&quot;666&quot;
</span></code></pre></div>
<p>Be sure to reload your udev rules after saving the file. On most distributions, this is accomplished with:</p>
<div class="language-bash highlight"><pre><span></span><code><span id="__span-6-1"><a id="__codelineno-6-1" name="__codelineno-6-1" href="#__codelineno-6-1"></a>udevadm<span class="w"> </span>control<span class="w"> </span>--reload-rules<span class="w"> </span><span class="o">&amp;&amp;</span><span class="w"> </span>udevadm<span class="w"> </span>trigger
<div class="language-bash highlight"><pre><span></span><code><span id="__span-5-1"><a id="__codelineno-5-1" name="__codelineno-5-1" href="#__codelineno-5-1"></a>udevadm<span class="w"> </span>control<span class="w"> </span>--reload-rules<span class="w"> </span><span class="o">&amp;&amp;</span><span class="w"> </span>udevadm<span class="w"> </span>trigger
</span></code></pre></div>
<h2 id="adding-manta-to-path-optional">Adding Manta to PATH (Optional)</h2>
<p>Although optional, it is convenient to add the <code>manta</code> executable to your system's path. This allows you to invoke Manta's CLI with <code>manta</code>, rather than the more verbose <code>python3 -m manta</code>. The location of this executable depends on both your platform and if you're using a virtual environment. For example:</p>
<ul>
<li>
<p>Windows: <code>%APPDATA%\Python\Scripts</code>, or <code>path\to\venv\Scripts</code> if using a virtual environment.</p>
</li>
<li>
<p>macOS/Linux/BSD: <code>$HOME/.local/bin</code>, or <code>path\to\venv\bin</code> if using a virtual environment.</p>
</li>
</ul>
<p>This also adds any other Python scripts exposed by your installed packages to your PATH.</p>
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fischermoseley/manta
@ -253,10 +255,15 @@
<span class="md-ellipsis">
Home
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@ -275,10 +282,15 @@
<span class="md-ellipsis">
Installation
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@ -319,10 +336,15 @@
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@ -341,10 +363,15 @@
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@ -363,10 +390,15 @@
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Similar Tools
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@ -403,10 +435,15 @@
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Cores
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@ -414,7 +451,11 @@
<nav class="md-nav" data-md-level="1" aria-labelledby="__nav_7_label" aria-expanded="true">
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<span class="md-nav__icon md-icon"></span>
Cores
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<ul class="md-nav__list" data-md-scrollfix>
@ -437,10 +478,15 @@
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IO Core
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@ -450,10 +496,15 @@
<span class="md-ellipsis">
IO Core
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@ -473,7 +524,9 @@
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<a href="#overview" class="md-nav__link">
<span class="md-ellipsis">
Overview
Overview
</span>
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@ -482,7 +535,9 @@
<li class="md-nav__item">
<a href="#configuration" class="md-nav__link">
<span class="md-ellipsis">
Configuration
Configuration
</span>
</a>
@ -492,7 +547,9 @@
<li class="md-nav__item">
<a href="#verilog-based-workflows" class="md-nav__link">
<span class="md-ellipsis">
Verilog-Based Workflows
Verilog-Based Workflows
</span>
</a>
@ -501,7 +558,9 @@
<li class="md-nav__item">
<a href="#amaranth-native-designs" class="md-nav__link">
<span class="md-ellipsis">
Amaranth-Native Designs
Amaranth-Native Designs
</span>
</a>
@ -515,7 +574,9 @@
<li class="md-nav__item">
<a href="#operation" class="md-nav__link">
<span class="md-ellipsis">
Operation
Operation
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</a>
@ -524,7 +585,9 @@
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<a href="#python-api-documentation" class="md-nav__link">
<span class="md-ellipsis">
Python API Documentation
Python API Documentation
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</a>
@ -534,7 +597,9 @@
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<a href="#manta.IOCore" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;IOCore
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;IOCore
</span>
</a>
@ -544,7 +609,9 @@
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<a href="#manta.IOCore.get_probe" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_probe
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_probe
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</a>
@ -553,7 +620,9 @@
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<a href="#manta.IOCore.set_probe" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_probe
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_probe
</span>
</a>
@ -590,10 +659,15 @@
<span class="md-ellipsis">
Logic Analyzer Core
</span>
</a>
</li>
@ -613,10 +687,15 @@
<span class="md-ellipsis">
Memory Core
</span>
</a>
</li>
@ -661,10 +740,15 @@
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Interfaces
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@ -672,7 +756,11 @@
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Interfaces
Interfaces
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@ -688,10 +776,15 @@
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UART Interface
</span>
</a>
</li>
@ -711,10 +804,15 @@
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Ethernet Interface
</span>
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@ -759,10 +857,15 @@
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For Developers
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@ -786,10 +893,15 @@
<span class="md-ellipsis">
Roadmap
</span>
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@ -831,7 +943,9 @@
<li class="md-nav__item">
<a href="#overview" class="md-nav__link">
<span class="md-ellipsis">
Overview
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</span>
</a>
@ -840,7 +954,9 @@
<li class="md-nav__item">
<a href="#configuration" class="md-nav__link">
<span class="md-ellipsis">
Configuration
Configuration
</span>
</a>
@ -850,7 +966,9 @@
<li class="md-nav__item">
<a href="#verilog-based-workflows" class="md-nav__link">
<span class="md-ellipsis">
Verilog-Based Workflows
Verilog-Based Workflows
</span>
</a>
@ -859,7 +977,9 @@
<li class="md-nav__item">
<a href="#amaranth-native-designs" class="md-nav__link">
<span class="md-ellipsis">
Amaranth-Native Designs
Amaranth-Native Designs
</span>
</a>
@ -873,7 +993,9 @@
<li class="md-nav__item">
<a href="#operation" class="md-nav__link">
<span class="md-ellipsis">
Operation
Operation
</span>
</a>
@ -882,7 +1004,9 @@
<li class="md-nav__item">
<a href="#python-api-documentation" class="md-nav__link">
<span class="md-ellipsis">
Python API Documentation
Python API Documentation
</span>
</a>
@ -892,7 +1016,9 @@
<li class="md-nav__item">
<a href="#manta.IOCore" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;IOCore
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;IOCore
</span>
</a>
@ -902,7 +1028,9 @@
<li class="md-nav__item">
<a href="#manta.IOCore.get_probe" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_probe
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_probe
</span>
</a>
@ -911,7 +1039,9 @@
<li class="md-nav__item">
<a href="#manta.IOCore.set_probe" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_probe
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_probe
</span>
</a>
@ -937,6 +1067,7 @@
<div class="md-content" data-md-component="content">
<article class="md-content__inner md-typeset">
@ -1015,6 +1146,7 @@ Inside this configuration, the following parameters may be set:</p>
<div class="doc doc-contents first">
<p>A synthesizable module for setting and getting the values of registers of
arbitrary size.</p>
@ -1062,7 +1194,9 @@ at least one probe, but it need not be an output.</p>
<div class="doc doc-children">
<div class="doc doc-children">
@ -1266,10 +1400,11 @@ or many probes were found with the same name.</p>
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@ -253,10 +255,15 @@
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@ -275,10 +282,15 @@
<span class="md-ellipsis">
Installation
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<span class="md-ellipsis">
Getting Started
</span>
</a>
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@ -319,10 +336,15 @@
<span class="md-ellipsis">
Use Cases
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</a>
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@ -341,10 +363,15 @@
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Architecture
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@ -505,7 +563,9 @@
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Configuration
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@ -515,7 +575,9 @@
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Verilog-Based Workflows
Verilog-Based Workflows
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</a>
@ -524,7 +586,9 @@
<li class="md-nav__item">
<a href="#triggers" class="md-nav__link">
<span class="md-ellipsis">
Triggers
Triggers
</span>
</a>
@ -533,7 +597,9 @@
<li class="md-nav__item">
<a href="#trigger-location-optional" class="md-nav__link">
<span class="md-ellipsis">
Trigger Location (optional)
Trigger Location (optional)
</span>
</a>
@ -542,7 +608,9 @@
<li class="md-nav__item">
<a href="#trigger-modes-optional" class="md-nav__link">
<span class="md-ellipsis">
Trigger Modes (optional)
Trigger Modes (optional)
</span>
</a>
@ -556,7 +624,9 @@
<li class="md-nav__item">
<a href="#usage" class="md-nav__link">
<span class="md-ellipsis">
Usage
Usage
</span>
</a>
@ -566,7 +636,9 @@
<li class="md-nav__item">
<a href="#capturing-data" class="md-nav__link">
<span class="md-ellipsis">
Capturing Data
Capturing Data
</span>
</a>
@ -575,7 +647,9 @@
<li class="md-nav__item">
<a href="#playback" class="md-nav__link">
<span class="md-ellipsis">
Playback
Playback
</span>
</a>
@ -589,7 +663,9 @@
<li class="md-nav__item">
<a href="#python-api-documentation" class="md-nav__link">
<span class="md-ellipsis">
Python API Documentation
Python API Documentation
</span>
</a>
@ -599,7 +675,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCore" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerCore
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerCore
</span>
</a>
@ -609,7 +687,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCore.capture" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;capture
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;capture
</span>
</a>
@ -618,7 +698,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCore.set_triggers" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_triggers
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_triggers
</span>
</a>
@ -632,7 +714,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerCapture
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerCapture
</span>
</a>
@ -642,7 +726,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.export_csv" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_csv
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_csv
</span>
</a>
@ -651,7 +737,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.export_playback_verilog" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_playback_verilog
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_playback_verilog
</span>
</a>
@ -660,7 +748,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.export_vcd" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_vcd
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_vcd
</span>
</a>
@ -669,7 +759,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.get_playback_module" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_playback_module
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_playback_module
</span>
</a>
@ -678,7 +770,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.get_trace" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_trace
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_trace
</span>
</a>
@ -687,7 +781,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.get_trigger_location" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_trigger_location
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_trigger_location
</span>
</a>
@ -701,7 +797,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerPlayback" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerPlayback
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerPlayback
</span>
</a>
@ -711,7 +809,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerPlayback.get_top_level_ports" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_top_level_ports
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_top_level_ports
</span>
</a>
@ -748,10 +848,15 @@
<span class="md-ellipsis">
Memory Core
</span>
</a>
</li>
@ -796,10 +901,15 @@
<span class="md-ellipsis">
Interfaces
</span>
<span class="md-nav__icon md-icon"></span>
</label>
@ -807,7 +917,11 @@
<nav class="md-nav" data-md-level="1" aria-labelledby="__nav_8_label" aria-expanded="false">
<label class="md-nav__title" for="__nav_8">
<span class="md-nav__icon md-icon"></span>
Interfaces
Interfaces
</label>
<ul class="md-nav__list" data-md-scrollfix>
@ -823,10 +937,15 @@
<span class="md-ellipsis">
UART Interface
</span>
</a>
</li>
@ -846,10 +965,15 @@
<span class="md-ellipsis">
Ethernet Interface
</span>
</a>
</li>
@ -894,10 +1018,15 @@
<span class="md-ellipsis">
For Developers
</span>
<span class="md-nav__icon md-icon"></span>
</label>
@ -905,7 +1034,11 @@
<nav class="md-nav" data-md-level="1" aria-labelledby="__nav_9_label" aria-expanded="false">
<label class="md-nav__title" for="__nav_9">
<span class="md-nav__icon md-icon"></span>
For Developers
For Developers
</label>
<ul class="md-nav__list" data-md-scrollfix>
@ -921,10 +1054,15 @@
<span class="md-ellipsis">
Roadmap
</span>
</a>
</li>
@ -966,7 +1104,9 @@
<li class="md-nav__item">
<a href="#overview" class="md-nav__link">
<span class="md-ellipsis">
Overview
Overview
</span>
</a>
@ -975,7 +1115,9 @@
<li class="md-nav__item">
<a href="#configuration" class="md-nav__link">
<span class="md-ellipsis">
Configuration
Configuration
</span>
</a>
@ -985,7 +1127,9 @@
<li class="md-nav__item">
<a href="#verilog-based-workflows" class="md-nav__link">
<span class="md-ellipsis">
Verilog-Based Workflows
Verilog-Based Workflows
</span>
</a>
@ -994,7 +1138,9 @@
<li class="md-nav__item">
<a href="#triggers" class="md-nav__link">
<span class="md-ellipsis">
Triggers
Triggers
</span>
</a>
@ -1003,7 +1149,9 @@
<li class="md-nav__item">
<a href="#trigger-location-optional" class="md-nav__link">
<span class="md-ellipsis">
Trigger Location (optional)
Trigger Location (optional)
</span>
</a>
@ -1012,7 +1160,9 @@
<li class="md-nav__item">
<a href="#trigger-modes-optional" class="md-nav__link">
<span class="md-ellipsis">
Trigger Modes (optional)
Trigger Modes (optional)
</span>
</a>
@ -1026,7 +1176,9 @@
<li class="md-nav__item">
<a href="#usage" class="md-nav__link">
<span class="md-ellipsis">
Usage
Usage
</span>
</a>
@ -1036,7 +1188,9 @@
<li class="md-nav__item">
<a href="#capturing-data" class="md-nav__link">
<span class="md-ellipsis">
Capturing Data
Capturing Data
</span>
</a>
@ -1045,7 +1199,9 @@
<li class="md-nav__item">
<a href="#playback" class="md-nav__link">
<span class="md-ellipsis">
Playback
Playback
</span>
</a>
@ -1059,7 +1215,9 @@
<li class="md-nav__item">
<a href="#python-api-documentation" class="md-nav__link">
<span class="md-ellipsis">
Python API Documentation
Python API Documentation
</span>
</a>
@ -1069,7 +1227,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCore" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerCore
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerCore
</span>
</a>
@ -1079,7 +1239,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCore.capture" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;capture
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;capture
</span>
</a>
@ -1088,7 +1250,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCore.set_triggers" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_triggers
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;set_triggers
</span>
</a>
@ -1102,7 +1266,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerCapture
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerCapture
</span>
</a>
@ -1112,7 +1278,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.export_csv" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_csv
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_csv
</span>
</a>
@ -1121,7 +1289,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.export_playback_verilog" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_playback_verilog
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_playback_verilog
</span>
</a>
@ -1130,7 +1300,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.export_vcd" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_vcd
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;export_vcd
</span>
</a>
@ -1139,7 +1311,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.get_playback_module" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_playback_module
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_playback_module
</span>
</a>
@ -1148,7 +1322,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.get_trace" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_trace
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_trace
</span>
</a>
@ -1157,7 +1333,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerCapture.get_trigger_location" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_trigger_location
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_trigger_location
</span>
</a>
@ -1171,7 +1349,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerPlayback" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerPlayback
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;LogicAnalyzerPlayback
</span>
</a>
@ -1181,7 +1361,9 @@
<li class="md-nav__item">
<a href="#manta.LogicAnalyzerPlayback.get_top_level_ports" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_top_level_ports
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;get_top_level_ports
</span>
</a>
@ -1207,6 +1389,7 @@
<div class="md-content" data-md-component="content">
<article class="md-content__inner md-typeset">
@ -1335,6 +1518,7 @@ The capture may be exported as either a VCD or CSV file. If <code>manta.yaml</co
<div class="doc doc-contents first">
<p>A module for generating a logic analyzer on the FPGA, with configurable
triggers, trigger position, and trigger modes.</p>
<p>Provides methods for generating synthesizable logic for the FPGA, as well
@ -1378,7 +1562,9 @@ a width.</p>
<div class="doc doc-children">
<div class="doc doc-children">
@ -1502,6 +1688,7 @@ containing the capture and its metadata.</p>
<div class="doc doc-contents first">
<p>A container class for the data collected by a LogicAnalyzerCore. Contains
methods for exporting the data as a VCD waveform file, a Python list, a
CSV file, or a Verilog module.</p>
@ -1515,7 +1702,9 @@ CSV file, or a Verilog module.</p>
<div class="doc doc-children">
<div class="doc doc-children">
@ -1749,6 +1938,7 @@ time of capture.</p>
<div class="doc doc-contents first">
<p>A synthesizable module that plays back data captured by a
LogicAnalyzerCore. Takes a list of all the samples captured by a core,
along with the config of the core used to take it.</p>
@ -1762,7 +1952,9 @@ along with the config of the core used to take it.</p>
<div class="doc doc-children">
<div class="doc doc-children">
@ -1848,10 +2040,11 @@ exported Verilog module.</p>
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@ -231,7 +233,7 @@
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@ -253,10 +255,15 @@
<span class="md-ellipsis">
Home
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@ -275,10 +282,15 @@
<span class="md-ellipsis">
Installation
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@ -297,10 +309,15 @@
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</a>
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@ -319,10 +336,15 @@
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</a>
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@ -341,10 +363,15 @@
<span class="md-ellipsis">
Architecture
</span>
</a>
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@ -363,10 +390,15 @@
<span class="md-ellipsis">
Similar Tools
</span>
</a>
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@ -403,10 +435,15 @@
<span class="md-ellipsis">
Cores
</span>
<span class="md-nav__icon md-icon"></span>
</label>
@ -414,7 +451,11 @@
<nav class="md-nav" data-md-level="1" aria-labelledby="__nav_7_label" aria-expanded="true">
<label class="md-nav__title" for="__nav_7">
<span class="md-nav__icon md-icon"></span>
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</label>
<ul class="md-nav__list" data-md-scrollfix>
@ -430,10 +471,15 @@
<span class="md-ellipsis">
IO Core
</span>
</a>
</li>
@ -453,10 +499,15 @@
<span class="md-ellipsis">
Logic Analyzer Core
</span>
</a>
</li>
@ -483,10 +534,15 @@
<span class="md-ellipsis">
Memory Core
</span>
<span class="md-nav__icon md-icon"></span>
</label>
@ -496,10 +552,15 @@
<span class="md-ellipsis">
Memory Core
</span>
</a>
@ -519,7 +580,9 @@
<li class="md-nav__item">
<a href="#overview" class="md-nav__link">
<span class="md-ellipsis">
Overview
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</span>
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@ -528,7 +591,9 @@
<li class="md-nav__item">
<a href="#on-chip-implementation" class="md-nav__link">
<span class="md-ellipsis">
On-Chip Implementation
On-Chip Implementation
</span>
</a>
@ -537,7 +602,9 @@
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<span class="md-ellipsis">
Configuration
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@ -547,7 +614,9 @@
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@ -556,7 +625,9 @@
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Amaranth-Native Designs
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@ -570,7 +641,9 @@
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@ -579,7 +652,9 @@
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@ -589,7 +664,9 @@
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<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;MemoryCore
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@ -599,7 +676,9 @@
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@ -608,7 +687,9 @@
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<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;write
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@ -670,10 +751,15 @@
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@ -681,7 +767,11 @@
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@ -697,10 +787,15 @@
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@ -720,10 +815,15 @@
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@ -768,10 +868,15 @@
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@ -779,7 +884,11 @@
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@ -795,10 +904,15 @@
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@ -840,7 +954,9 @@
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<span class="md-ellipsis">
Overview
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</span>
</a>
@ -849,7 +965,9 @@
<li class="md-nav__item">
<a href="#on-chip-implementation" class="md-nav__link">
<span class="md-ellipsis">
On-Chip Implementation
On-Chip Implementation
</span>
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@ -858,7 +976,9 @@
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<span class="md-ellipsis">
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</span>
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@ -868,7 +988,9 @@
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<span class="md-ellipsis">
Verilog-Based Workflows
Verilog-Based Workflows
</span>
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@ -877,7 +999,9 @@
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<span class="md-ellipsis">
Amaranth-Native Designs
Amaranth-Native Designs
</span>
</a>
@ -891,7 +1015,9 @@
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<a href="#operation" class="md-nav__link">
<span class="md-ellipsis">
Operation
Operation
</span>
</a>
@ -900,7 +1026,9 @@
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<a href="#python-api-documentation" class="md-nav__link">
<span class="md-ellipsis">
Python API Documentation
Python API Documentation
</span>
</a>
@ -910,7 +1038,9 @@
<li class="md-nav__item">
<a href="#manta.MemoryCore" class="md-nav__link">
<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;MemoryCore
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;MemoryCore
</span>
</a>
@ -920,7 +1050,9 @@
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<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;read
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</span>
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@ -929,7 +1061,9 @@
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<span class="md-ellipsis">
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;write
<code class="doc-symbol doc-symbol-toc doc-symbol-method"></code>&nbsp;write
</span>
</a>
@ -955,6 +1089,7 @@
<div class="md-content" data-md-component="content">
<article class="md-content__inner md-typeset">
@ -1019,6 +1154,7 @@
<div class="doc doc-contents first">
<p>A synthesizable module for accessing a memory. This is accomplished by
instantiating a dual-port memory with one end tied to Manta's internal bus,
and the other provided to user logic.</p>
@ -1071,7 +1207,9 @@ is available on nearly all platforms.</p>
<div class="doc doc-children">
<div class="doc doc-children">
@ -1270,10 +1408,11 @@ fit within the width of the memory.</p>
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@ -253,10 +255,15 @@
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@ -458,7 +505,9 @@
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Xilinx Integrated Logic Analyzer
Xilinx Integrated Logic Analyzer
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@ -467,7 +516,9 @@
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@ -476,7 +527,9 @@
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Intel Signal Tap
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@ -588,10 +658,15 @@
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@ -611,10 +686,15 @@
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@ -634,10 +714,15 @@
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@ -709,10 +803,15 @@
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@ -913,7 +1043,9 @@
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@ -922,7 +1054,9 @@
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@ -931,7 +1065,9 @@
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@ -958,7 +1098,9 @@
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<loc>https://fischermoseley.github.io/manta/dev/logic_analyzer_core/</loc>
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@ -253,10 +255,15 @@
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@ -275,10 +282,15 @@
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@ -297,10 +309,15 @@
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Getting Started
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@ -319,10 +336,15 @@
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Use Cases
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@ -341,10 +363,15 @@
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Architecture
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@ -363,10 +390,15 @@
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Similar Tools
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@ -403,10 +435,15 @@
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Cores
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@ -414,7 +451,11 @@
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Cores
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@ -430,10 +471,15 @@
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IO Core
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@ -453,10 +499,15 @@
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Logic Analyzer Core
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@ -476,10 +527,15 @@
<span class="md-ellipsis">
Memory Core
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@ -524,10 +580,15 @@
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@ -535,7 +596,11 @@
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Interfaces
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@ -558,10 +623,15 @@
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UART Interface
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@ -571,10 +641,15 @@
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UART Interface
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@ -594,7 +669,9 @@
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@ -603,7 +680,9 @@
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@ -613,7 +692,9 @@
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Verilog-Based Workflows
Verilog-Based Workflows
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@ -622,7 +703,9 @@
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@ -631,7 +714,9 @@
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<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;UARTInterface
<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;UARTInterface
</span>
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@ -663,10 +748,15 @@
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Ethernet Interface
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@ -783,7 +887,9 @@
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Overview
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</span>
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@ -792,7 +898,9 @@
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@ -802,7 +910,9 @@
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Verilog-Based Workflows
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@ -811,7 +921,9 @@
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Amaranth-Native Designs
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@ -820,7 +932,9 @@
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<code class="doc-symbol doc-symbol-toc doc-symbol-class"></code>&nbsp;UARTInterface
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</span>
</a>
@ -841,6 +955,7 @@
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<article class="md-content__inner md-typeset">
@ -908,6 +1023,7 @@ Inside this configuration, the following parameters may be set:</p>
<div class="doc doc-contents first">
<p>A synthesizable module for UART communication between a host machine and
the FPGA.</p>
@ -1007,7 +1123,9 @@ provided, or the clock frequency or baudrate is invalid.</p>
<div class="doc doc-children">
<div class="doc doc-children">
@ -1072,10 +1190,11 @@ provided, or the clock frequency or baudrate is invalid.</p>
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fischermoseley/manta
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Home
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Installation
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Getting Started
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Use Cases
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Logic Analyzer Core
Logic Analyzer Core
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I/O Core
I/O Core
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Memory Cores
Memory Cores
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Architecture
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Similar Tools
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Cores
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Cores
Cores
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IO Core
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Logic Analyzer Core
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Memory Core
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Interfaces
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Interfaces
Interfaces
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UART Interface
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Ethernet Interface
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Roadmap
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Logic Analyzer Core
Logic Analyzer Core
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I/O Core
I/O Core
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Memory Cores
Memory Cores
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