move macro functions to tasks, update to

test/functional_sim/block_memory_tb.sv

@@ -50,7 +50,7 @@ task write_and_verify_bus_side(
 
     write_reg_bus_side(addr, write_data);
     read_reg_bus_side(addr, read_data);
-    assert(read_data == write_data) else $error("data read does not match data written!");
+    assert(read_data == write_data) else $fatal(0, "data read does not match data written!");
 endtask
 
 task read_user_side(

test/functional_sim/bridge_rx_tb.sv

@@ -1,51 +1,58 @@
 `default_nettype none
-`timescale 1ns/1ps
+// `timescale 1ns/1ps
 
 `define CP 10
 `define HCP 5
 
-`define SEND_MESSAGE(MESSAGE) \
+task test_good_read_msg (
-    tb_brx_valid = 1; \
+    input string message,
-    for(int i=0; i < $size(MESSAGE); i++) begin \
+    input [15:0] addr
-        tb_brx_data = MESSAGE[i]; \
+    );
-        #`CP; \
-    end \
-    tb_brx_valid = 0; \
 
-`define TEST_GOOD_READ_MSG(MESSAGE, ADDR) \
+    bridge_rx_tb.tb_brx_valid = 1;
-    tb_brx_valid = 1; \
+    for(int i=0; i < $size(message); i++) begin
-    for(int i=0; i < $size(MESSAGE); i++) begin \
+        bridge_rx_tb.tb_brx_data = message [i];
-        tb_brx_data = MESSAGE[i]; \
+        if(bridge_rx_tb.brx_tb_valid) begin
-        if(brx_tb_valid) begin \
+            assert(bridge_rx_tb.brx_tb_addr == addr) else $fatal(0, "wrong addr!");
-            assert(brx_tb_addr == ADDR) else $error("wrong addr!"); \
+            assert(bridge_rx_tb.brx_tb_rw == 0) else $fatal(0, "wrong rw!");
-            assert(brx_tb_rw == 0) else $error("wrong rw!");        \
+            assert(bridge_rx_tb.brx_tb_data == 0) else $fatal(0, "wrong data!");
-            assert(brx_tb_data == 0) else $error("wrong data!");    \
+        end
-        end \
+        #`CP;
-        #`CP; \
+    end
-    end \
+    bridge_rx_tb.tb_brx_valid = 0;
-    tb_brx_valid = 0; \
+endtask
 
-`define TEST_GOOD_WRITE_MSG(MESSAGE, ADDR, DATA) \
+task test_good_write_msg (
-    tb_brx_valid = 1; \
+    input string message,
-    for(int i=0; i < $size(MESSAGE); i++) begin \
+    input [15:0] addr,
-        tb_brx_data = MESSAGE[i]; \
+    input [15:0] data
-        if(brx_tb_valid) begin \
+    );
-            assert(brx_tb_addr == ADDR) else $error("wrong addr!"); \
-            assert(brx_tb_rw == 1) else $error("wrong rw!");        \
-            assert(brx_tb_data == DATA) else $error("wrong data!"); \
-        end \
-        #`CP; \
-    end \
-    tb_brx_valid = 0; \
 
-`define TEST_BAD_MSG(MESSAGE) \
+    bridge_rx_tb.tb_brx_valid = 1;
-    tb_brx_valid = 1; \
+    for(int i=0; i < $size(message); i++) begin
-    for(int i=0; i < $size(MESSAGE); i++) begin \
+        bridge_rx_tb.tb_brx_data = message[i];
-        tb_brx_data = MESSAGE[i]; \
+        if(bridge_rx_tb.brx_tb_valid) begin
-        assert(brx_tb_valid == 0) else $error("wrong valid!"); \
+            assert(bridge_rx_tb.brx_tb_addr == addr) else $fatal(0, "wrong addr!");
-        #`CP; \
+            assert(bridge_rx_tb.brx_tb_rw == 1) else $fatal(0, "wrong rw!");
-    end \
+            assert(bridge_rx_tb.brx_tb_data == data) else $fatal(0, "wrong data!");
-    tb_brx_valid = 0; \
+        end
+        #`CP;
+    end
+    bridge_rx_tb.tb_brx_valid = 0;
+endtask
+
+task test_bad_msg (
+    input string message
+    );
+
+    bridge_rx_tb.tb_brx_valid = 1;
+    for(int i=0; i < $size(message); i++) begin
+        bridge_rx_tb.tb_brx_data = message[i];
+        assert(bridge_rx_tb.brx_tb_valid == 0) else $fatal(0, "wrong valid!");
+        #`CP;
+    end
+    bridge_rx_tb.tb_brx_valid = 0;
+endtask
 
 
 module bridge_rx_tb;
@@ -53,7 +60,6 @@ module bridge_rx_tb;
 
 //boilerplate
 logic clk;
-string message;
 integer test_num;
 
 // uart inputs and outputs
@@ -95,96 +101,80 @@ initial begin
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit W12345678(CR)(LF) for baseline functionality ===", test_num);
-    message = {"W12345678", 8'h0D, 8'h0A};
+    test_good_write_msg("W12345678\r\n", 16'h1234, 16'h5678);
-    `TEST_GOOD_WRITE_MSG(message, 16'h1234, 16'h5678)
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit WDEADBEEF(CR)(LF) for proper state reset ===", test_num);
-    message = {"WDEADBEEF", 8'h0D, 8'h0A};
+    test_good_write_msg("WDEADBEEF\r\n", 16'hDEAD, 16'hBEEF);
-    `TEST_GOOD_WRITE_MSG(message, 16'hDEAD, 16'hBEEF)
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit RBABE(CR)(LF) for baseline functionality ===", test_num);
-    message = {"RBABE", 8'h0D, 8'h0A};
+    test_good_read_msg("RBABE\r\n", 16'hBABE);
-    `TEST_GOOD_READ_MSG(message, 16'hBABE);
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit R0000(CR) for EOL insensitivity ===", test_num);
-    message = {"R0000", 8'h0D};
+    test_good_read_msg("R0000\r", 16'hBABE);
-    `TEST_GOOD_READ_MSG(message, 16'hBABE);
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit R1234(LF) for EOL insensitivity ===", test_num);
-    message = {"R1234", 8'h0D};
+    test_good_read_msg("R1234\n", 16'h1234);
-    `TEST_GOOD_READ_MSG(message, 16'h1234);
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit WF00DBEEF(CR) for EOL insensitivity ===", test_num);
-    message = {"WF00DBEEF", 8'h0D};
+    test_good_write_msg("WF00DBEEF\r", 16'hF00D, 16'hBEEF);
-    `TEST_GOOD_WRITE_MSG(message, 16'hF00D, 16'hBEEF);
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit WB0BACAFE(LF) for EOL insensitivity ===", test_num);
-    message = {"WB0BACAFE", 8'h0D};
+    test_good_write_msg("WB0BACAFE\r", 16'hB0BA, 16'hCAFE);
-    `TEST_GOOD_WRITE_MSG(message, 16'hB0BA, 16'hCAFE)
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit R1234(LF)R5678 for back-to-back messages ===", test_num);
-    message = {"R1234", 8'h0D, 8'h0A};
+    test_good_read_msg("R1234\r\n", 16'h1234);
-    `TEST_GOOD_READ_MSG(message, 16'h1234)
+    test_good_read_msg("R5678\r\n", 16'h5678);
-    message = {"R5678", 8'h0D, 8'h0A};
-    `TEST_GOOD_READ_MSG(message, 16'h5678)
     #(10*`CP);
 
     $display("\n\nIntentionally bad messages:");
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit RABC(CR)(LF) for message length ===", test_num);
-    message = {"RABC", 8'h0D, 8'h0A};
+    test_bad_msg("RABC\r\n");
-    `TEST_BAD_MSG(message);
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit R12345(CR)(LF) for message length ===", test_num);
-    message = {"RABC", 8'h0D, 8'h0A};
+    test_bad_msg("R12345\r\n");
-    `TEST_BAD_MSG(message)
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit M(CR)(LF) for message length ===", test_num);
-    message = {"WABC", 8'h0D, 8'h0A};
+    test_bad_msg("WABC\r\n");
-    `TEST_BAD_MSG(message)
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit W123456789101112131415161718191201222(CR)(LF) for message length ===", test_num);
-    message = {"W123456789101112131415161718191201222", 8'h0D, 8'h0A};
+    test_bad_msg("W123456789101112131415161718191201222\r\n");
-    `TEST_BAD_MSG(message)
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit RABCG(CR)(LF) for invalid characters ===", test_num);
-    message = {"RABCG", 8'h0D, 8'h0A};
+    test_bad_msg("RABCG\r\n");
-    `TEST_BAD_MSG(message)
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit WABC[]()##*@(CR)(LF) for invalid characters and message length ===", test_num);
-    message = {"WABC[]()##*@", 8'h0D, 8'h0A};
+    test_bad_msg("WABC[]()##*@\r\n");
-    `TEST_BAD_MSG(message)
     #(10*`CP);
 
     test_num = test_num + 1;
     $display("\n=== test %2d: transmit R(CR)(LF) for message length ===", test_num);
-    message = {"R", 8'h0D, 8'h0A};
+    test_bad_msg("R\r\n");
-    `TEST_BAD_MSG(message)
     #(10*`CP);
 
     $finish();

test/functional_sim/bridge_tx_tb.sv

@@ -71,7 +71,7 @@ initial begin
     tb_btx_valid = 1;
 
     #`CP;
-    assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
+    assert(res_ready == 0) else $fatal(0, "invalid handshake: res_ready held high for more than one clock cycle");
     tb_btx_valid = 0;
 
     #(100000*`CP);
@@ -84,7 +84,7 @@ initial begin
     tb_btx_valid = 1;
 
     #`CP;
-    assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
+    assert(res_ready == 0) else $fatal(0, "invalid handshake: res_ready held high for more than one clock cycle");
     tb_btx_valid = 0;
 
     #(100000*`CP);
@@ -97,7 +97,7 @@ initial begin
     tb_btx_valid = 1;
 
     #`CP;
-    assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
+    assert(res_ready == 0) else $fatal(0, "invalid handshake: res_ready held high for more than one clock cycle");
     tb_btx_valid = 0;
 
     #(100000*`CP);
@@ -110,7 +110,7 @@ initial begin
     tb_btx_valid = 1;
 
     #`CP;
-    assert(res_ready == 0) else $error("invalid handshake: res_ready held high for more than one clock cycle");
+    assert(res_ready == 0) else $fatal(0, "invalid handshake: res_ready held high for more than one clock cycle");
     tb_btx_valid = 0;
 
     #(100000*`CP);

test/functional_sim/ethernet_rx_tb.sv

@@ -89,7 +89,7 @@ module ethernet_rx_tb();
 
         //     #1000;
 
-        //     assert(mrx_payload == i) else $error("data mismatch!");
+        //     assert(mrx_payload == i) else $fatal(0, "data mismatch!");
         // end
         $finish();
     end

test/functional_sim/ethernet_tx_tb.sv

@@ -112,7 +112,7 @@ module ethernet_tx_tb();
 
         //     #1000;
 
-        //     assert(mrx_payload == i) else $error("data mismatch!");
+        //     assert(mrx_payload == i) else $fatal(0, "data mismatch!");
         // end
         $finish();
     end

test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv

@@ -47,7 +47,7 @@ task write_and_verify(
 
     write_reg(addr, write_data, desc);
     read_reg(addr, read_data, desc);
-    assert(read_data == write_data) else $error("data read does not match data written!");
+    assert(read_data == write_data) else $fatal(0, "data read does not match data written!");
 endtask
 
 task read_all_reg();
@@ -229,7 +229,7 @@ module logic_analyzer_tb;
         // write_and_verify(10, 3, "shemp_arg"); // set argument to 3
 
         // assert( (la.fsm_registers.state == la.la_controller.IDLE) || (la.fsm_registers.state == la.la_controller.CAPTURED) )
-        //     else $error("core is running when it shouldn't be!");
+        //     else $fatal(0, "core is running when it shouldn't be!");
 
         // larry = 0;
         // curly = 0;

test/functional_sim/lut_mem_tb.sv

@@ -148,10 +148,10 @@ module lut_mem_tb;
 
         // TODO: make this check that all bus outputs are 0
 
-        // assert(req_addr == 16'h1234) else $error("incorrect addr!");
+        // assert(req_addr == 16'h1234) else $fatal(0, "incorrect addr!");
-        // assert(req_data == 16'h5678) else $error("incorrect data!");
+        // assert(req_data == 16'h5678) else $fatal(0, "incorrect data!");
-        // assert(req_rw == 1) else $error("incorrect rw!");
+        // assert(req_rw == 1) else $fatal(0, "incorrect rw!");
-        // assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $error("in error state after transmission");
+        // assert(bridge_rx_uut.state != bridge_rx_uut.ERROR) else $fatal(0, "in error state after transmission");
 
         tb_mem_1_addr = 16'h0001;
         tb_mem_1_valid = 1;

test/functional_sim/mac_tb.sv

@@ -77,7 +77,7 @@ module mac_tb();
 
             #1000;
 
-            assert(mrx_payload == i) else $error("data mismatch!");
+            assert(mrx_payload == i) else $fatal(0, "data mismatch!");
         end
         $finish();
     end