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switch playback to synchronous read ports, make things synthesizable

This commit is contained in:
Fischer Moseley 2023-12-28 21:46:44 -08:00
parent 90a5dba665
commit d31aa2650e
1 changed files with 15 additions and 8 deletions
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23
src/manta/logic_analyzer_core.py
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@ -509,7 +509,7 @@ class LogicAnalyzerPlayback(Elaboratable):
# State Machine # State Machine
self.start = Signal(1) self.start = Signal(1)
self.idle = Signal(1, reset=1) self.valid = Signal(1)
# Top-Level Probe signals # Top-Level Probe signals
self.top_level_probes = {} self.top_level_probes = {}
@ -523,32 +523,39 @@ class LogicAnalyzerPlayback(Elaboratable):
init=self.data, init=self.data,
) )
self.read_port = self.mem.read_port(domain="comb") self.read_port = self.mem.read_port()
def elaborate(self, platform): def elaborate(self, platform):
m = Module() m = Module()
m.submodules["mem"] = self.mem m.submodules["mem"] = self.mem
# Run state machine m.d.comb += self.read_port.en.eq(1)
with m.If(self.idle):
# State Machine
busy = Signal(1)
with m.If(~busy):
with m.If(self.start): with m.If(self.start):
m.d.sync += self.idle.eq(0) m.d.sync += busy.eq(1)
# m.d.sync += self.read_port.addr.eq(1)
with m.Else(): with m.Else():
with m.If(self.read_port.addr == self.config["sample_depth"] - 1): with m.If(self.read_port.addr == self.config["sample_depth"] - 1):
m.d.sync += self.idle.eq(1) m.d.sync += busy.eq(0)
m.d.sync += self.read_port.addr.eq(0) m.d.sync += self.read_port.addr.eq(0)
with m.Else(): with m.Else():
m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1) m.d.sync += self.read_port.addr.eq(self.read_port.addr + 1)
# Pipeline to accomodate for the 2-cycle latency in the RAM
m.d.sync += self.valid.eq(busy)
# Assign the probe values by part-selecting from the data port # Assign the probe values by part-selecting from the data port
lower = 0 lower = 0
for name, width in reversed(self.config["probes"].items()): for name, width in reversed(self.config["probes"].items()):
signal = self.top_level_probes[name] signal = self.top_level_probes[name]
# Set output probe to zero if we're not # Set output probe to zero if we're not
with m.If(~self.idle): with m.If(self.valid):
m.d.comb += signal.eq(self.read_port.data[lower : lower + width]) m.d.comb += signal.eq(self.read_port.data[lower : lower + width])
with m.Else(): with m.Else():
@ -559,4 +566,4 @@ class LogicAnalyzerPlayback(Elaboratable):
return m return m
def get_top_level_ports(self): def get_top_level_ports(self):
return [self.start, self.idle] + list(self.top_level_probes.values()) return [self.start, self.valid] + list(self.top_level_probes.values())