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put test outputs in build/

This commit is contained in:
Fischer Moseley 2024-03-06 16:40:54 -08:00
parent 6900087237
commit bd452d94a4
2 changed files with 18 additions and 7 deletions
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17
src/manta/utils.py
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@ -2,7 +2,8 @@ from amaranth import *
from amaranth.lib import data from amaranth.lib import data
from amaranth.sim import Simulator from amaranth.sim import Simulator
from abc import ABC, abstractmethod from abc import ABC, abstractmethod
from random import sample, randint from random import sample
from pathlib import Path
import os import os
@ -114,22 +115,30 @@ def split_into_chunks(data, chunk_size):
return [data[i : i + chunk_size] for i in range(0, len(data), chunk_size)] return [data[i : i + chunk_size] for i in range(0, len(data), chunk_size)]
def make_build_dir_if_it_does_not_exist_already():
"""
Make build/ if it doesn't exist already.
"""
Path("build").mkdir(parents=True, exist_ok=True)
def simulate(top): def simulate(top):
""" """
A decorator for running behavioral simulation using Amaranth's built-in A decorator for running behavioral simulation using Amaranth's built-in
simulator. Requires the top-level module in the simulation as an argument, simulator. Requires the top-level module in the simulation as an argument,
and automatically names VCD file containing the waveform dump with the name and automatically names VCD file containing the waveform dump in build/
of the function being decorated. with the name of the function being decorated.
""" """
def decorator(testbench): def decorator(testbench):
make_build_dir_if_it_does_not_exist_already()
def wrapper(*args, **kwargs): def wrapper(*args, **kwargs):
sim = Simulator(top) sim = Simulator(top)
sim.add_clock(1e-6) # 1 MHz sim.add_clock(1e-6) # 1 MHz
sim.add_sync_process(testbench) sim.add_sync_process(testbench)
vcd_path = testbench.__name__ + ".vcd" vcd_path = "build/" + testbench.__name__ + ".vcd"
with sim.write_vcd(vcd_path): with sim.write_vcd(vcd_path):
sim.run() sim.run()

8
test/test_logic_analyzer_hw.py
View File

@ -59,14 +59,16 @@ class LogicAnalyzerCounterTest(Elaboratable):
self.build_and_program() self.build_and_program()
cap = self.manta.la.capture() cap = self.manta.la.capture()
make_build_dir_if_it_does_not_exist_already()
# check that VCD export works # check that VCD export works
cap.export_vcd("out.vcd") cap.export_vcd("build/logic_analyzer_capture.vcd")
# check that CSV export works # check that CSV export works
cap.export_csv("out.csv") cap.export_csv("build/logic_analyzer_capture.csv")
# check that Verilog export works # check that Verilog export works
cap.export_playback_verilog("out.v") cap.export_playback_verilog("build/logic_analzyer_capture_playback.v")
# verify that each signal is just a counter modulo the width of the signal # verify that each signal is just a counter modulo the width of the signal
for name, width in self.manta.la._config["probes"].items(): for name, width in self.manta.la._config["probes"].items():