tests: include building examples in test suite

examples/amaranth/uart_io_core.py

@@ -65,6 +65,7 @@ class UARTIOCoreExample(Elaboratable):
 # board. This means that by changing which platform you pass UARTIOCoreExample
 # below, you can port this example to any FPGA board!
 
-from amaranth_boards.icestick import ICEStickPlatform
+if __name__ == "__main__":
+    from amaranth_boards.icestick import ICEStickPlatform
 
-UARTIOCoreExample(platform=ICEStickPlatform(), port="auto").test()
+    UARTIOCoreExample(platform=ICEStickPlatform(), port="auto").test()

examples/amaranth/uart_logic_analyzer.py

@@ -68,9 +68,7 @@ class UARTLogicAnalyzerExample(Elaboratable):
 # board. This means that by changing which platform you pass UARTIOCoreExample
 # below, you can port this example to any FPGA board!
 
-from amaranth_boards.icestick import ICEStickPlatform
+if __name__ == "__main__":
+    from amaranth_boards.icestick import ICEStickPlatform
 
-UARTLogicAnalyzerExample(
+    UARTLogicAnalyzerExample(platform=ICEStickPlatform(), port="auto").test()
-    platform=ICEStickPlatform(),
-    port="/dev/serial/by-id/usb-Lattice_Lattice_FTUSB_Interface_Cable-if01-port0",
-).test()

examples/amaranth/uart_memory_core.py

@@ -63,9 +63,10 @@ class UARTMemoryCoreExample(Elaboratable):
 # board. This means that by changing which platform you pass UARTIOCoreExample
 # below, you can port this example to any FPGA board!
 
-from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
+if __name__ == "__main__":
+    from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
 
-UARTMemoryCoreExample(
+    UARTMemoryCoreExample(
-    platform=Nexys4DDRPlatform(),
+        platform=Nexys4DDRPlatform(),
-    port="auto",
+        port="auto",
-).test()
+    ).test()

examples/verilog/icestick/uart_io_core/build.sh

@@ -1,3 +1,6 @@
+#!/usr/bin/env bash
+set -e
+
 python3 -m manta gen manta.yaml manta.v
 $YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
 $NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc

examples/verilog/icestick/uart_logic_analyzer/build.sh

@@ -1,3 +1,6 @@
+#!/usr/bin/env bash
+set -e
+
 python3 -m manta gen manta.yaml manta.v
 $YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
 $NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc

examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core/build.sh

@@ -1,3 +1,6 @@
+#!/usr/bin/env bash
+set -e
+
 python3 -m manta gen manta.yaml manta.v
 mkdir -p build/
 $VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/build.sh

@@ -1,3 +1,6 @@
+#!/usr/bin/env bash
+set -e
+
 python3 -m manta gen manta.yaml manta.v
 mkdir -p build/
 $VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/uart_io_core/build.sh

@@ -1,3 +1,6 @@
+#!/usr/bin/env bash
+set -e
+
 python3 -m manta gen manta.yaml manta.v
 mkdir -p build/
 $VIVADO -mode batch -source build.tcl

examples/verilog/nexys4_ddr/uart_logic_analyzer/build.sh

@@ -1,3 +1,6 @@
+#!/usr/bin/env bash
+set -e
+
 python3 -m manta gen manta.yaml manta.v
 mkdir -p build/
 $VIVADO -mode batch -source build.tcl

test/test_examples_build.py

@@ -0,0 +1,57 @@
+import subprocess
+import pytest
+import sys
+import os
+
+verilog_root_dirs = [
+    "examples/verilog/icestick/uart_io_core",
+    "examples/verilog/icestick/uart_logic_analyzer",
+    "examples/verilog/nexys4_ddr/ether_logic_analyzer_io_core",
+    "examples/verilog/nexys4_ddr/uart_host_to_fpga_mem",
+    "examples/verilog/nexys4_ddr/uart_io_core",
+    "examples/verilog/nexys4_ddr/uart_logic_analyzer",
+]
+
+
+@pytest.mark.parametrize("root_dir", verilog_root_dirs)
+def test_verilog_examples_build(root_dir):
+    result = subprocess.run(
+        ["./build.sh"], cwd=root_dir, capture_output=True, text=True
+    )
+
+    if result.returncode != 0:
+        raise ValueError(f"Command failed with return code {result.returncode}.")
+
+
+# Patch the PATH variable so imports from examples/ are possible
+parent_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
+sys.path.insert(0, parent_dir)
+
+# Import Examples
+from examples.amaranth.uart_io_core import UARTIOCoreExample
+from examples.amaranth.uart_logic_analyzer import UARTLogicAnalyzerExample
+from examples.amaranth.uart_memory_core import UARTMemoryCoreExample
+
+# Import Platforms
+from amaranth_boards.icestick import ICEStickPlatform
+from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
+
+# Manually specify a list of examples/platforms to test.
+
+# This is necessary as some examples don't work without some amount of onboard
+# IO - for instance, the UARTMemoryCore example requires switches and LEDs to
+# read out the memory provided by Manta, but the Icestick doesn't have any
+# switches.
+amaranth_examples_cases = [
+    (UARTIOCoreExample, ICEStickPlatform),
+    (UARTIOCoreExample, Nexys4DDRPlatform),
+    (UARTLogicAnalyzerExample, ICEStickPlatform),
+    (UARTLogicAnalyzerExample, Nexys4DDRPlatform),
+    (UARTMemoryCoreExample, Nexys4DDRPlatform),
+]
+
+
+@pytest.mark.parametrize("example, platform", amaranth_examples_cases)
+def test_amaranth_examples_build(example, platform):
+    design = example(platform(), port="auto")
+    design.platform.build(design, do_program=False)