revert wiring.Component instead of Elaboratable

src/manta/ethernet/__init__.py

@@ -1,6 +1,4 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from manta.utils import *
 from manta.ethernet.source_bridge import UDPSourceBridge
 from manta.ethernet.sink_bridge import UDPSinkBridge
@@ -8,7 +6,7 @@ from random import randint
 import socket
 
 
-class EthernetInterface(wiring.Component):
+class EthernetInterface(Elaboratable):
     """
     A module for communicating with Manta over Ethernet, using UDP.
 

src/manta/ethernet/sink_bridge.py

@@ -1,10 +1,8 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from manta.utils import *
 
 
-class UDPSinkBridge(wiring.Component):
+class UDPSinkBridge(Elaboratable):
     """
     A module for bridging Manta's internal bus to an AXI stream of UDP packet
     data. Connects to the LiteEth core's "sink" port.

src/manta/ethernet/source_bridge.py

@@ -1,10 +1,8 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from manta.utils import *
 
 
-class UDPSourceBridge(wiring.Component):
+class UDPSourceBridge(Elaboratable):
     """
     A module for bridging the AXI-stream of incoming UDP packet data to Manta's
     internal bus. Connects to the LiteEth core's "source" port.

src/manta/logic_analyzer/__init__.py

@@ -1,6 +1,4 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from manta.utils import *
 from manta.memory_core import MemoryCore
 from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock

src/manta/logic_analyzer/fsm.py

@@ -1,6 +1,4 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from amaranth.lib.enum import IntEnum
 from manta.io_core import IOCore
 
@@ -19,7 +17,7 @@ class TriggerModes(IntEnum):
     IMMEDIATE = 2
 
 
-class LogicAnalyzerFSM(wiring.Component):
+class LogicAnalyzerFSM(Elaboratable):
     """
     A module containing the state machine for a LogicAnalyzerCore. Primarily
     responsible for controlling the write port of the Logic Analyzer's sample

src/manta/logic_analyzer/playback.py

@@ -1,9 +1,7 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 
 
-class LogicAnalyzerPlayback(wiring.Component):
+class LogicAnalyzerPlayback(Elaboratable):
     """
     A synthesizable module that plays back data captured by a
     LogicAnalyzerCore. Takes a list of all the samples captured by a core,

src/manta/logic_analyzer/trigger_block.py

@@ -1,11 +1,9 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from amaranth.lib.enum import IntEnum
 from manta.io_core import IOCore
 
 
-class LogicAnalyzerTriggerBlock(wiring.Component):
+class LogicAnalyzerTriggerBlock(Elaboratable):
     """
     A module containing an instance of a LogicAnalyzerTrigger for each input
     probe. The operations and arguments of these LogicAnalyzerTriggers are set
@@ -88,7 +86,7 @@ class Operations(IntEnum):
     NEQ = 9
 
 
-class LogicAnalyzerTrigger(wiring.Component):
+class LogicAnalyzerTrigger(Elaboratable):
     """
     A module containing a programmable "trigger" for a given input signal,
     which asserts its output when the programmed "trigger condition" is met.

src/manta/manta.py

@@ -1,6 +1,4 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from manta.uart import UARTInterface
 from manta.ethernet import EthernetInterface
 from manta.io_core import IOCore
@@ -8,7 +6,7 @@ from manta.memory_core import MemoryCore
 from manta.logic_analyzer import LogicAnalyzerCore
 
 
-class Manta(wiring.Component):
+class Manta(Elaboratable):
     def __init__(self, config):
         # Load config from either a configuration file or a dictionary.
         # Users primarily use the config file, but the dictionary is

src/manta/memory_core.py

@@ -1,6 +1,4 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from manta.utils import *
 from math import ceil
 

src/manta/uart/__init__.py

@@ -1,6 +1,4 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from manta.utils import *
 from manta.uart.receiver import UARTReceiver
 from manta.uart.receive_bridge import ReceiveBridge
@@ -9,7 +7,7 @@ from manta.uart.transmit_bridge import TransmitBridge
 from serial import Serial
 
 
-class UARTInterface(wiring.Component):
+class UARTInterface(Elaboratable):
     """
     A module for communicating with Manta over UART.
 

src/manta/uart/receive_bridge.py

@@ -1,6 +1,4 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from amaranth.lib.enum import IntEnum
 from amaranth.lib.data import ArrayLayout
 
@@ -11,7 +9,7 @@ class States(IntEnum):
     WRITE = 2
 
 
-class ReceiveBridge(wiring.Component):
+class ReceiveBridge(Elaboratable):
     """
     A module for bridging the stream of bytes from the UARTReceiver module to
     Manta's internal bus.

src/manta/uart/receiver.py

@@ -1,9 +1,7 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 
 
-class UARTReceiver(wiring.Component):
+class UARTReceiver(Elaboratable):
     """
     A module for receiving bytes on a 8N1 UART at a configurable baudrate.
     Outputs bytes as a stream.

src/manta/uart/transmit_bridge.py

@@ -1,9 +1,7 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 
 
-class TransmitBridge(wiring.Component):
+class TransmitBridge(Elaboratable):
     """
     A module for bridging Manta's internal bus to the stream of bytes expected
     by the UARTTransmitter module.

src/manta/uart/transmitter.py

@@ -1,9 +1,7 @@
 from amaranth import *
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 
 
-class UARTTransmitter(wiring.Component):
+class UARTTransmitter(Elaboratable):
     """
     A module for transmitting bytes on a 8N1 UART at a configurable baudrate.
     Accepts bytes as a stream.

src/manta/utils.py

@@ -1,14 +1,12 @@
 from amaranth import *
 from amaranth.lib import data
-from amaranth.lib import wiring
-from amaranth.lib.wiring import In, Out
 from amaranth.sim import Simulator
 from abc import ABC, abstractmethod
 from random import sample
 import os
 
 
-class MantaCore(ABC, wiring.Component):
+class MantaCore(ABC, Elaboratable):
 
     @property
     @abstractmethod

test/test_io_core_hw.py

@@ -7,7 +7,7 @@ import pytest
 from random import randint
 
 
-class IOCoreLoopbackTest(wiring.Component):
+class IOCoreLoopbackTest(Elaboratable):
     def __init__(self, platform, port):
         self.platform = platform
         self.port = port

test/test_logic_analyzer_hw.py

@@ -6,7 +6,7 @@ from manta.utils import *
 import pytest
 
 
-class LogicAnalyzerCounterTest(wiring.Component):
+class LogicAnalyzerCounterTest(Elaboratable):
     def __init__(self, platform, port):
         self.platform = platform
         self.port = port

test/test_mem_core_hw.py

@@ -14,7 +14,7 @@ configuration, or a standard one.
 """
 
 
-class MemoryCoreLoopbackTest(wiring.Component):
+class MemoryCoreLoopbackTest(Elaboratable):
     def __init__(self, platform, width, depth, port):
         self.platform = platform
         self.width = width

test/test_mem_core_sim.py

@@ -28,7 +28,6 @@ class MemoryCoreTests:
         for addr in self.user_addrs:
             yield from self.verify_user_side(addr, 0)
 
-
     def one_bus_write_then_one_bus_read(self):
         for addr in self.bus_addrs:
             data_width = self.get_data_width(addr)
@@ -64,7 +63,6 @@ class MemoryCoreTests:
                     self.model[addr] = data
                     yield from self.write_bus_side(addr, data)
 
-
     def one_user_write_then_one_bus_read(self):
         for user_addr in self.user_addrs:
             # write to user side
@@ -121,7 +119,6 @@ class MemoryCoreTests:
                     for addr, word in zip(bus_addrs, words):
                         self.model[addr] = word
 
-
     def one_bus_write_then_one_user_read(self):
         yield
 
@@ -131,7 +128,6 @@ class MemoryCoreTests:
     def rand_bus_writes_rand_user_reads(self):
         yield
 
-
     def one_user_write_then_one_user_read(self):
         for addr in self.user_addrs:
             data = randint(0, (2**self.width) - 1)