luke
/
manta
mirror of https://github.com/fischermoseley/manta.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

meta: use InternalBusLayout instead of InternalBus()

This commit is contained in:
Fischer Moseley 2026-03-08 13:49:45 -06:00
parent f61b4ca2b6
commit a7bd7d20b2
3 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/manta/ethernet/__init__.py
View File

@ -70,8 +70,8 @@ class EthernetInterface(Elaboratable):
self._additional_config = kwargs self._additional_config = kwargs
self._check_config() self._check_config()
self.bus_i = Signal(InternalBus()) self.bus_i = Signal(InternalBusLayout)
self.bus_o = Signal(InternalBus()) self.bus_o = Signal(InternalBusLayout)
# Define PHY IO, assuming that we're in a Verilog-based workflow. # Define PHY IO, assuming that we're in a Verilog-based workflow.
self._define_phy_io(self._phy) self._define_phy_io(self._phy)

4
src/manta/io_core.py
View File

@ -34,8 +34,8 @@ class IOCore(MantaCore):
self._outputs = outputs self._outputs = outputs
# Bus Connections # Bus Connections
self.bus_i = Signal(InternalBus()) self.bus_i = Signal(InternalBusLayout)
self.bus_o = Signal(InternalBus()) self.bus_o = Signal(InternalBusLayout)
# Internal Signals # Internal Signals
self._strobe = Signal() self._strobe = Signal()

4
src/manta/logic_analyzer/__init__.py
View File

@ -41,8 +41,8 @@ class LogicAnalyzerCore(MantaCore):
self._triggers = [] self._triggers = []
# Bus Input/Output # Bus Input/Output
self.bus_i = Signal(InternalBus()) self.bus_i = Signal(InternalBusLayout)
self.bus_o = Signal(InternalBus()) self.bus_o = Signal(InternalBusLayout)
@property @property
def max_addr(self): def max_addr(self):