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replace logic nettype with reg

This commit is contained in:
Fischer Moseley 2023-07-09 18:23:04 -07:00
parent 38f7ee86fa
commit 9771d80fd1
2 changed files with 4 additions and 4 deletions
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2
src/manta/ether_iface/crc32.v
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@ -28,7 +28,7 @@ module crc32(
output reg axiov, output reg axiov,
output reg [31:0] axiod); output reg [31:0] axiod);
logic[31:0] caxiod, saxiod; reg [31:0] caxiod, saxiod;
initial caxiod = 32'hFFFF_FFFF; initial caxiod = 32'hFFFF_FFFF;
integer i; integer i;

6
src/manta/ether_iface/firewall.v
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@ -20,12 +20,12 @@ module firewall (
/* Buffers to hold our MAC address in the reverse order, /* Buffers to hold our MAC address in the reverse order,
* to make comparison easier than it otherwise would be * to make comparison easier than it otherwise would be
*/ */
logic[0:47] me; reg [0:47] me;
/* A counter, to determine whether we should be comparing /* A counter, to determine whether we should be comparing
* with a MAC address or stripping off data * with a MAC address or stripping off data
*/ */
logic[31:0] counter; reg [31:0] counter;
/* An internal set of flags to mark whether the currently /* An internal set of flags to mark whether the currently
* traversing packet is valid, i.e we should forward data, * traversing packet is valid, i.e we should forward data,
@ -36,7 +36,7 @@ module firewall (
* destination MAC finishes rolling through, the packet * destination MAC finishes rolling through, the packet
* is forwarded. * is forwarded.
*/ */
logic matchme, matchbcast; reg matchme, matchbcast;
assign me = FPGA_MAC; assign me = FPGA_MAC;