manta: fix code generation from config file, update tests
This commit is contained in:
Fischer Moseley
parent
3ba93efd2f
commit
8f45546b5a
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@ -1,16 +1,16 @@
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from manta import Manta
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from manta import *
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from time import sleep
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manta = Manta("manta.yaml")
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manta = Manta.from_config("manta.yaml")
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i = 0
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while True:
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# Turn each LED off
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for j in range(5):
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manta.my_io_core.set_probe(f"LED{j}", 0)
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manta.cores.my_io_core.set_probe(f"LED{j}", 0)
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# Turn one LED back on
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manta.my_io_core.set_probe(f"LED{i}", 1)
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manta.cores.my_io_core.set_probe(f"LED{i}", 1)
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i = (i + 1) % 5
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sleep(0.1)
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@ -1,6 +1,6 @@
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from manta import Manta
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from manta import *
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m = Manta("manta.yaml")
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manta = Manta.from_config("manta.yaml")
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print(m.my_io_core.get_probe("sw"))
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m.my_io_core.set_probe("led", 4)
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print(manta.cores.my_io_core.get_probe("sw"))
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manta.cores.my_io_core.set_probe("led", 4)
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@ -1,8 +1,8 @@
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from manta import Manta
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from manta import *
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m = Manta("manta.yaml")
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manta = Manta.from_config("manta.yaml")
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# Memory addresses can be written to in Python, and then be read out by
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# flipping the switches on the FPGA, and watching the LEDs update!
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m.my_memory.write(0, 1)
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manta.cores.my_memory.write(0, 1)
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@ -1,25 +1,25 @@
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from manta import Manta
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from manta import *
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from time import sleep
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from random import randint
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m = Manta("manta.yaml")
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manta = Manta.from_config("manta.yaml")
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i = 0
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while True:
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i = (i + 1) % 16
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m.my_io_core.set_probe("led", 2**i)
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manta.cores.my_io_core.set_probe("led", 2**i)
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m.my_io_core.set_probe("led16_r", randint(0, 1))
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m.my_io_core.set_probe("led16_g", randint(0, 1))
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m.my_io_core.set_probe("led16_b", randint(0, 1))
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manta.cores.my_io_core.set_probe("led16_r", randint(0, 1))
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manta.cores.my_io_core.set_probe("led16_g", randint(0, 1))
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manta.cores.my_io_core.set_probe("led16_b", randint(0, 1))
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print(f'Switches: {m.my_io_core.get_probe("sw")}')
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print(f'Switches: {manta.cores.my_io_core.get_probe("sw")}')
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print(f"Buttons:")
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print(f'btnu: {m.my_io_core.get_probe("btnu")}')
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print(f'btnd: {m.my_io_core.get_probe("btnd")}')
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print(f'btnr: {m.my_io_core.get_probe("btnr")}')
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print(f'btnl: {m.my_io_core.get_probe("btnl")}')
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print(f'btnc: {m.my_io_core.get_probe("btnc")}')
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print(f'btnu: {manta.cores.my_io_core.get_probe("btnu")}')
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print(f'btnd: {manta.cores.my_io_core.get_probe("btnd")}')
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print(f'btnr: {manta.cores.my_io_core.get_probe("btnr")}')
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print(f'btnl: {manta.cores.my_io_core.get_probe("btnl")}')
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print(f'btnc: {manta.cores.my_io_core.get_probe("btnc")}')
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print("")
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sleep(0.1)
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@ -69,13 +69,13 @@ def wrong_args():
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def gen(config_path, output_path):
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m = Manta(config_path)
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m.generate_verilog(output_path)
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manta = Manta.from_config(config_path)
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manta.generate_verilog(output_path)
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def inst(config_path):
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m = Manta(config_path)
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ports = m.get_top_level_ports()
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manta = Manta.from_config(config_path)
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ports = manta.get_top_level_ports()
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hdl = ",\n ".join([f".{p.name}({p.name})" for p in ports])
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foo = """
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@ -88,8 +88,8 @@ manta manta_inst(
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def capture(config_path, logic_analyzer_name, export_paths):
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m = Manta(config_path)
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la = getattr(m, logic_analyzer_name)
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manta = Manta.from_config(config_path)
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la = getattr(manta.cores, logic_analyzer_name)
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cap = la.capture()
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for path in export_paths:
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@ -22,7 +22,7 @@ class EthernetInterface(Elaboratable):
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self._host_ip_addr = host_ip_addr
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self._udp_port = udp_port
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self._phy = phy
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self._clk_freq = clk_freq
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self._clk_freq = float(clk_freq)
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self._additional_config = kwargs
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self._check_config()
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@ -81,6 +81,10 @@ class EthernetInterface(Elaboratable):
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if not 0 <= int(byte) <= 255:
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raise ValueError(f"Invalid byte in FPGA IP: {byte}")
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@classmethod
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def from_config(cls, config):
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return EthernetInterface(**config)
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def to_config(self):
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config = {
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"fpga_ip_addr": self._fpga_ip_addr,
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@ -40,7 +40,7 @@ class IOCore(MantaCore):
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return self._max_addr
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@classmethod
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def from_config(cls, config, base_addr, interface):
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def from_config(cls, config):
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inputs = config.get("inputs", {})
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outputs = config.get("outputs", {})
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@ -117,7 +117,7 @@ class IOCore(MantaCore):
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output_signals += [Signal(width, name=name, init=initial_value)]
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return cls(base_addr, interface, inputs=input_signals, outputs=output_signals)
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return cls(inputs=input_signals, outputs=output_signals)
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def to_config(self):
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config = {}
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@ -5,6 +5,8 @@ from manta.io_core import IOCore
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from manta.memory_core import MemoryCore
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from manta.logic_analyzer import LogicAnalyzerCore
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from manta.utils import *
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import yaml
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import json
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class Manta(Elaboratable):
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@ -25,117 +27,61 @@ class Manta(Elaboratable):
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for core in self.cores._cores.values():
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core.interface = value
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# def __init__(self, config):
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# # Load config from either a configuration file or a dictionary.
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# # Users primarily use the config file, but the dictionary is
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# # included for internal tests.
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@classmethod
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def from_config(cls, config_path):
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# if isinstance(config, str):
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# self._config = self._read_config_file(config)
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# Load config from either YAML or JSON
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extension = config_path.split(".")[-1]
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if extension not in ["yaml", "yml", "json"]:
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raise ValueError(f"Configuration file {config_path} has unrecognized file type.")
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# if isinstance(config, dict):
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# self._config = config
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with open(config_path, "r") as f:
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if extension in ["yaml", "yml"]:
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config = yaml.safe_load(f)
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# self._check_config()
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elif extension in ["json"]:
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config = json.load(f)
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# self._get_interface()
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# self._get_cores()
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# self._add_friendly_core_names()
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# Validate config
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if "cores" not in config:
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raise ValueError("No cores specified in configuration file.")
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# def _read_config_file(self, path):
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# """
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# Takes a path to configuration file, and return the configuration as a
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# python dictionary.
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# """
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if not len(config["cores"]) > 0:
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raise ValueError("Must specify at least one core.")
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# extension = path.split(".")[-1]
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for name, attrs in config["cores"].items():
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# Make sure core type is specified
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if "type" not in attrs:
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raise ValueError(f"No type specified for core {name}.")
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# if "json" in extension:
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# import json
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# with open(path, "r") as f:
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# return json.load(f)
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if attrs["type"] not in ["logic_analyzer", "io", "memory"]:
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raise ValueError(f"Unrecognized core type specified for {name}.")
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# elif "yaml" in extension or "yml" in extension:
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# import yaml
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# with open(path, "r") as f:
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# return yaml.safe_load(f)
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# Make Manta object, and configure it
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manta = Manta()
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# else:
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# raise ValueError("Unable to recognize configuration file extension.")
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# Add interface
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if "uart" in config:
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manta.interface = UARTInterface.from_config(config["uart"])
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# def _check_config(self):
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# if "cores" not in self._config:
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# raise ValueError("No cores specified in configuration file.")
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elif "ethernet" in config:
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manta.interface = EthernetInterface.from_config(config["ethernet"])
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# if not len(self._config["cores"]) > 0:
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# raise ValueError("Must specify at least one core.")
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# Add cores
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for name, attrs in config["cores"].items():
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if attrs["type"] == "io":
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core = IOCore.from_config(attrs)
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# for name, attrs in self._config["cores"].items():
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# # Make sure core type is specified
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# if "type" not in attrs:
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# raise ValueError(f"No type specified for core {name}.")
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elif attrs["type"] == "logic_analyzer":
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core = LogicAnalyzerCore.from_config(attrs)
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# if attrs["type"] not in ["logic_analyzer", "io", "memory"]:
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# raise ValueError(f"Unrecognized core type specified for {name}.")
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elif attrs["type"] == "memory":
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core = MemoryCore.from_config(attrs)
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# def _get_interface(self):
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# """
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# Returns an instance of an interface object (UARTInterface or
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# EthernetInterface) configured with the parameters in the
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# config file.
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# """
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# if "uart" in self._config:
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# self.interface = UARTInterface.from_config(self._config["uart"])
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setattr(manta.cores, name, core)
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# elif "ethernet" in self._config:
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# self.interface = EthernetInterface(self._config["ethernet"])
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return manta
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# else:
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# raise ValueError("No recognized interface specified.")
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# def _get_cores(self):
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# """
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# Creates instances of the cores (IOCore, LogicAnalyzerCore, MemoryCore)
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# specified in the user's configuration, and returns them as a list.
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# """
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# self._cores = {}
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# base_addr = 0
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# for name, attrs in self._config["cores"].items():
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# if attrs["type"] == "io":
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# core = IOCore.from_config(attrs, base_addr, self.interface)
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# elif attrs["type"] == "logic_analyzer":
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# core = LogicAnalyzerCore(attrs, base_addr, self.interface)
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# elif attrs["type"] == "memory":
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# core = MemoryCore.from_config(attrs, base_addr, self.interface)
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# # Make sure we're not out of address space
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# if core.max_addr > (2**16) - 1:
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# raise ValueError(
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# f"Ran out of address space to allocate to core {name}."
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# )
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# # Make the next core's base address start one address after the previous one's
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# base_addr = core.max_addr + 1
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# self._cores[name] = core
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# def _add_friendly_core_names(self):
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# """
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# Add cores to the instance under a friendly name - ie, a core named `my_core` belonging
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# to a Manta instance `m` could be obtained with `m.cores["my_core"]`, but this allows
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# it to be obtained with `m.my_core`. Which is way nicer.
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# """
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# for name, instance in self._cores.items():
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# if not hasattr(self, name):
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# setattr(self, name, instance)
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# else:
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# raise ValueError(
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# "Cannot add object to Manta instance - name is already taken!"
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# )
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def elaborate(self, platform):
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m = Module()
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@ -88,7 +88,7 @@ class MemoryCore(MantaCore):
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}
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@classmethod
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def from_config(cls, config, base_addr, interface):
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def from_config(cls, config):
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# Check for unrecognized options
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valid_options = ["type", "depth", "width", "mode"]
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for option in config:
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@ -125,7 +125,7 @@ class MemoryCore(MantaCore):
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if mode not in ["fpga_to_host", "host_to_fpga", "bidirectional"]:
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raise ValueError("Unrecognized mode provided to memory core.")
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return cls(mode, width, depth, base_addr, interface)
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return cls(mode, width, depth)
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def _tie_mems_to_bus(self, m):
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for i, mem in enumerate(self._mems):
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@ -76,6 +76,10 @@ class CoreContainer:
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self._cores[name] = value
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value.interface = self._manta.interface
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value.base_addr = self._last_used_addr
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if value.max_addr > (2**16)-1:
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raise ValueError(f"Ran out of address space while allocating core.")
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self._last_used_addr = value.max_addr + 1
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