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ethernet: use context manager to read generated LiteEth Verilog

This commit is contained in:
Fischer Moseley 2026-01-14 14:56:22 -07:00
parent 5d614127cf
commit 8d319e9e76
1 changed files with 2 additions and 5 deletions
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7
src/manta/ethernet/liteeth_gen.py
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@ -664,8 +664,5 @@ def main(core_config):
builder = Builder(soc, compile_gateware=False, output_dir=path) builder = Builder(soc, compile_gateware=False, output_dir=path)
builder.build(build_name="liteeth_core") builder.build(build_name="liteeth_core")
file = open(path + "/gateware/liteeth_core.v") with open(path + "/gateware/liteeth_core.v") as f:
data = file.read() return f.read()
file.close()
return data