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update examples, which appear to build :cowboy:

This commit is contained in:
Fischer Moseley 2023-07-19 09:37:18 -07:00
parent 0840786914
commit 8b9abd1b0b
11 changed files with 575 additions and 21 deletions
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193
examples/nexys_a7/io_core_ether/src/divider.sv Normal file
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`default_nettype wire
// file: divider.sv
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// popopopopopopopopopopop
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// __ethclk__50.00000______0.000______50.0______151.636_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module divider
(// Clock in ports
// Clock out ports
output ethclk,
input clk
);
// Input buffering
//------------------------------------
wire clk_divider;
wire clk_in2_divider;
IBUF clkin1_ibufg
(.O (clk_divider),
.I (clk));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire ethclk_divider;
wire clk_out2_divider;
wire clk_out3_divider;
wire clk_out4_divider;
wire clk_out5_divider;
wire clk_out6_divider;
wire clk_out7_divider;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_divider;
wire clkfbout_buf_divider;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_divider),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (ethclk_divider),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_divider),
.CLKIN1 (clk_divider),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_divider),
.I (clkfbout_divider));
BUFG clkout1_buf
(.O (ethclk),
.I (ethclk_divider));
endmodule
`default_nettype none

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examples/nexys_a7/io_core_ether/src/ssd.v
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../common/ssd.v

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`default_nettype none
`timescale 1ns/1ps
module ssd (
input wire clk,
input wire [31:0] val,
output reg [6:0] cat,
output reg [7:0] an);
parameter COUNT_TO = 100000;
reg [7:0] segment_state = 8'b0000_0001;
reg [31:0] segment_counter = 32'b0;
reg [3:0] digit;
reg [6:0] led_out;
bto7s mbto7s (
.x_in(digit),
.s_out(led_out));
assign cat = ~led_out;
assign an = ~segment_state;
always @(*) begin
case(segment_state)
8'b0000_0001: digit = val[3:0];
8'b0000_0010: digit = val[7:4];
8'b0000_0100: digit = val[11:8];
8'b0000_1000: digit = val[15:12];
8'b0001_0000: digit = val[19:16];
8'b0010_0000: digit = val[23:20];
8'b0100_0000: digit = val[27:24];
8'b1000_0000: digit = val[31:28];
default: digit = val[3:0];
endcase
end
always @(posedge clk) begin
segment_counter <= segment_counter + 1;
if (segment_counter == COUNT_TO) begin
segment_counter <= 32'd0;
segment_state <= {segment_state[6:0], segment_state[7]};
end
end
endmodule
module bto7s (
input wire [3:0] x_in,
output reg [6:0] s_out);
reg sa, sb, sc, sd, se, sf, sg;
assign s_out = {sg, sf, se, sd, sc, sb, sa};
// array of bits that are "one hot" with numbers 0 through 15
reg [15:0] num;
genvar i;
generate
for(i=0; i<16; i=i+1)
assign num[i] = (x_in == i);
endgenerate
// map one-hot bits to active segments
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
assign se = (num & 16'b1111_1101_0100_0101) > 0;
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
endmodule
`default_nettype wire

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examples/nexys_a7/io_core_uart/src/ssd.v
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../common/ssd.v

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examples/nexys_a7/io_core_uart/src/ssd.v Normal file
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`default_nettype none
`timescale 1ns/1ps
module ssd (
input wire clk,
input wire [31:0] val,
output reg [6:0] cat,
output reg [7:0] an);
parameter COUNT_TO = 100000;
reg [7:0] segment_state = 8'b0000_0001;
reg [31:0] segment_counter = 32'b0;
reg [3:0] digit;
reg [6:0] led_out;
bto7s mbto7s (
.x_in(digit),
.s_out(led_out));
assign cat = ~led_out;
assign an = ~segment_state;
always @(*) begin
case(segment_state)
8'b0000_0001: digit = val[3:0];
8'b0000_0010: digit = val[7:4];
8'b0000_0100: digit = val[11:8];
8'b0000_1000: digit = val[15:12];
8'b0001_0000: digit = val[19:16];
8'b0010_0000: digit = val[23:20];
8'b0100_0000: digit = val[27:24];
8'b1000_0000: digit = val[31:28];
default: digit = val[3:0];
endcase
end
always @(posedge clk) begin
segment_counter <= segment_counter + 1;
if (segment_counter == COUNT_TO) begin
segment_counter <= 32'd0;
segment_state <= {segment_state[6:0], segment_state[7]};
end
end
endmodule
module bto7s (
input wire [3:0] x_in,
output reg [6:0] s_out);
reg sa, sb, sc, sd, se, sf, sg;
assign s_out = {sg, sf, se, sd, sc, sb, sa};
// array of bits that are "one hot" with numbers 0 through 15
reg [15:0] num;
genvar i;
generate
for(i=0; i<16; i=i+1)
assign num[i] = (x_in == i);
endgenerate
// map one-hot bits to active segments
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
assign se = (num & 16'b1111_1101_0100_0101) > 0;
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
endmodule
`default_nettype wire

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examples/nexys_a7/lut_mem_ether/src/ssd.v
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../common/ssd.v

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examples/nexys_a7/lut_mem_ether/src/ssd.v Normal file
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`default_nettype none
`timescale 1ns/1ps
module ssd (
input wire clk,
input wire [31:0] val,
output reg [6:0] cat,
output reg [7:0] an);
parameter COUNT_TO = 100000;
reg [7:0] segment_state = 8'b0000_0001;
reg [31:0] segment_counter = 32'b0;
reg [3:0] digit;
reg [6:0] led_out;
bto7s mbto7s (
.x_in(digit),
.s_out(led_out));
assign cat = ~led_out;
assign an = ~segment_state;
always @(*) begin
case(segment_state)
8'b0000_0001: digit = val[3:0];
8'b0000_0010: digit = val[7:4];
8'b0000_0100: digit = val[11:8];
8'b0000_1000: digit = val[15:12];
8'b0001_0000: digit = val[19:16];
8'b0010_0000: digit = val[23:20];
8'b0100_0000: digit = val[27:24];
8'b1000_0000: digit = val[31:28];
default: digit = val[3:0];
endcase
end
always @(posedge clk) begin
segment_counter <= segment_counter + 1;
if (segment_counter == COUNT_TO) begin
segment_counter <= 32'd0;
segment_state <= {segment_state[6:0], segment_state[7]};
end
end
endmodule
module bto7s (
input wire [3:0] x_in,
output reg [6:0] s_out);
reg sa, sb, sc, sd, se, sf, sg;
assign s_out = {sg, sf, se, sd, sc, sb, sa};
// array of bits that are "one hot" with numbers 0 through 15
reg [15:0] num;
genvar i;
generate
for(i=0; i<16; i=i+1)
assign num[i] = (x_in == i);
endgenerate
// map one-hot bits to active segments
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
assign se = (num & 16'b1111_1101_0100_0101) > 0;
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
endmodule
`default_nettype wire

8
examples/nexys_a7/lut_mem_ether/src/top_level.sv
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@ -41,10 +41,10 @@ module top_level (
reg rw_latched = 0;
always @(posedge clk) begin
if (manta.brx_my_lut_mem_valid) begin
addr_latched <= manta.my_lut_mem_brx_addr;
data_latched <= manta.my_lut_mem_brx_data;
rw_latched <= manta.my_lut_mem_btx_rw;
if (manta_inst.brx_my_lut_mem_valid) begin
addr_latched <= manta_inst.my_lut_mem_brx_addr;
data_latched <= manta_inst.my_lut_mem_brx_data;
rw_latched <= manta_inst.my_lut_mem_btx_rw;
end
end

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examples/nexys_a7/lut_mem_uart/src/ssd.v
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../common/ssd.v

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examples/nexys_a7/lut_mem_uart/src/ssd.v Normal file
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`default_nettype none
`timescale 1ns/1ps
module ssd (
input wire clk,
input wire [31:0] val,
output reg [6:0] cat,
output reg [7:0] an);
parameter COUNT_TO = 100000;
reg [7:0] segment_state = 8'b0000_0001;
reg [31:0] segment_counter = 32'b0;
reg [3:0] digit;
reg [6:0] led_out;
bto7s mbto7s (
.x_in(digit),
.s_out(led_out));
assign cat = ~led_out;
assign an = ~segment_state;
always @(*) begin
case(segment_state)
8'b0000_0001: digit = val[3:0];
8'b0000_0010: digit = val[7:4];
8'b0000_0100: digit = val[11:8];
8'b0000_1000: digit = val[15:12];
8'b0001_0000: digit = val[19:16];
8'b0010_0000: digit = val[23:20];
8'b0100_0000: digit = val[27:24];
8'b1000_0000: digit = val[31:28];
default: digit = val[3:0];
endcase
end
always @(posedge clk) begin
segment_counter <= segment_counter + 1;
if (segment_counter == COUNT_TO) begin
segment_counter <= 32'd0;
segment_state <= {segment_state[6:0], segment_state[7]};
end
end
endmodule
module bto7s (
input wire [3:0] x_in,
output reg [6:0] s_out);
reg sa, sb, sc, sd, se, sf, sg;
assign s_out = {sg, sf, se, sd, sc, sb, sa};
// array of bits that are "one hot" with numbers 0 through 15
reg [15:0] num;
genvar i;
generate
for(i=0; i<16; i=i+1)
assign num[i] = (x_in == i);
endgenerate
// map one-hot bits to active segments
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
assign se = (num & 16'b1111_1101_0100_0101) > 0;
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
endmodule
`default_nettype wire

8
examples/nexys_a7/lut_mem_uart/src/top_level.sv
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@ -26,10 +26,10 @@ module top_level (
reg rw_latched = 0;
always @(posedge clk) begin
if (manta.brx_my_lut_mem_valid) begin
addr_latched <= manta.my_lut_mem_brx_addr;
data_latched <= manta.my_lut_mem_brx_data;
rw_latched <= manta.my_lut_mem_btx_rw;
if (manta_inst.brx_my_lut_mem_valid) begin
addr_latched <= manta_inst.my_lut_mem_brx_addr;
data_latched <= manta_inst.my_lut_mem_brx_data;
rw_latched <= manta_inst.my_lut_mem_btx_rw;
end
end

2
examples/nexys_a7/ps2_logic_analyzer/sim/playback.v
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@ -1,5 +1,5 @@
/*
This playback module was generated with Manta v0.0.5 on 17 Jul 2023 at 07:28:30 by fischerm
This playback module was generated with Manta v0.0.5 on 19 Jul 2023 at 09:22:12 by fischerm
If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu

1
examples/nexys_a7/video_sprite_ether/manta.yaml
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@ -7,3 +7,4 @@ cores:
ethernet:
interface: "en8"
host_mac: "12:34:56:78:90:ab"

1
examples/nexys_a7/video_sprite_uart/src/ssd.v
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@ -1 +0,0 @@
../../common/ssd.v

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examples/nexys_a7/video_sprite_uart/src/ssd.v Normal file
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@ -0,0 +1,73 @@
`default_nettype none
`timescale 1ns/1ps
module ssd (
input wire clk,
input wire [31:0] val,
output reg [6:0] cat,
output reg [7:0] an);
parameter COUNT_TO = 100000;
reg [7:0] segment_state = 8'b0000_0001;
reg [31:0] segment_counter = 32'b0;
reg [3:0] digit;
reg [6:0] led_out;
bto7s mbto7s (
.x_in(digit),
.s_out(led_out));
assign cat = ~led_out;
assign an = ~segment_state;
always @(*) begin
case(segment_state)
8'b0000_0001: digit = val[3:0];
8'b0000_0010: digit = val[7:4];
8'b0000_0100: digit = val[11:8];
8'b0000_1000: digit = val[15:12];
8'b0001_0000: digit = val[19:16];
8'b0010_0000: digit = val[23:20];
8'b0100_0000: digit = val[27:24];
8'b1000_0000: digit = val[31:28];
default: digit = val[3:0];
endcase
end
always @(posedge clk) begin
segment_counter <= segment_counter + 1;
if (segment_counter == COUNT_TO) begin
segment_counter <= 32'd0;
segment_state <= {segment_state[6:0], segment_state[7]};
end
end
endmodule
module bto7s (
input wire [3:0] x_in,
output reg [6:0] s_out);
reg sa, sb, sc, sd, se, sf, sg;
assign s_out = {sg, sf, se, sd, sc, sb, sa};
// array of bits that are "one hot" with numbers 0 through 15
reg [15:0] num;
genvar i;
generate
for(i=0; i<16; i=i+1)
assign num[i] = (x_in == i);
endgenerate
// map one-hot bits to active segments
assign sa = (num & 16'b1101_0111_1110_1101) > 0;
assign sb = (num & 16'b0010_0111_1001_1111) > 0;
assign sc = (num & 16'b0010_1111_1111_1011) > 0;
assign sd = (num & 16'b0111_1011_0110_1101) > 0;
assign se = (num & 16'b1111_1101_0100_0101) > 0;
assign sf = (num & 16'b1101_1111_0111_0001) > 0;
assign sg = (num & 16'b1110_1111_0111_1100) > 0;
endmodule
`default_nettype wire

12
examples/nexys_a7/video_sprite_uart/src/top_level.sv
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@ -97,16 +97,16 @@
reg [15:0] data_latched = 0;
reg rw_latched = 0;
always @(posedge clk) begin
if (manta.brx_image_mem_valid) begin
addr_latched <= manta.image_mem_brx_addr;
data_latched <= manta.image_mem_brx_data;
rw_latched <= manta.image_mem_btx_rw;
always @(posedge clk_65mhz) begin
if (manta_inst.brx_image_mem_valid) begin
addr_latched <= manta_inst.brx_image_mem_addr;
data_latched <= manta_inst.brx_image_mem_data;
rw_latched <= manta_inst.brx_image_mem_rw;
end
end
ssd ssd (
.clk(clk),
.clk(clk_65mhz),
.val( (addr_latched << 16) | (data_latched) ),
.cat({cg,cf,ce,cd,cc,cb,ca}),
.an(an));