tidy up mac stack

test/functional_sim/mac_tb.sv

@@ -1,6 +1,11 @@
 `default_nettype none
 `timescale 1ns/1ps
 
+`define FPGA_MAC 48'h69_69_5A_06_54_91
+`define HOST_MAC 48'h00_E0_4C_68_1E_0C
+`define ETHERTYPE 16'h88_B5
+
+
 module mac_tb();
     logic clk;
 
@@ -15,19 +20,24 @@ module mac_tb();
     logic txen;
     logic [1:0] txd;
 
-    logic [15:0] mtx_data;
-    logic [15:0] mtx_ethertype;
+    // this testbench makes sure that our rx pipeline is good,
+    // so we'll have mtx simulate the host machine and blast
+    // 5 bytes (plus padding) onto our fake RMII
+    logic [39:0] mtx_payload;
     logic mtx_start;
 
-    logic [15:0] mrx_data;
-    logic [15:0] mrx_ethertype;
+    logic [39:0] mrx_payload;
     logic mrx_valid;
 
-    mac_tx mtx (
+    mac_tx #(
+        .SRC_MAC(`HOST_MAC),
+        .DST_MAC(`FPGA_MAC),
+        .ETHERTYPE(`ETHERTYPE),
+        .PAYLOAD_LENGTH_BYTES(5)
+    ) mtx (
         .clk(clk),
 
-        .data(mtx_data),
-        .ethertype(mtx_ethertype),
+        .payload(mtx_payload),
         .start(mtx_start),
 
         .txen(txen),
@@ -36,28 +46,28 @@ module mac_tb();
     assign rxd = txd;
     assign crsdv = txen;
 
-    mac_rx mrx (
+    mac_rx #(
+        .FPGA_MAC(`FPGA_MAC),
+        .ETHERTYPE(`ETHERTYPE)
+    ) mrx (
         .clk(clk),
 
         .crsdv(crsdv),
         .rxd(rxd),
 
-        .data(mrx_data),
-        .ethertype(mrx_ethertype),
+        .payload(mrx_payload),
         .valid(mrx_valid));
 
     initial begin
         $dumpfile("mac_tb.vcd");
         $dumpvars(0, mac_tb);
         clk = 0;
-        mtx_ethertype = 0;
-        mtx_data = 0;
+        mtx_payload = 0;
         mtx_start = 0;
         #10;
 
-        for (int i=0; i<128; i=i+1) begin
-            mtx_data = i;
-            mtx_ethertype = i;
+        for (int i=0; i<32; i=i+1) begin
+            mtx_payload = i;
             mtx_start = 0;
             #10;
             mtx_start = 1;
@@ -67,7 +77,7 @@ module mac_tb();
 
             #1000;
 
-            assert(mrx_data == i) else $error("data mismatch!");
+            assert(mrx_payload == i) else $error("data mismatch!");
         end
         $finish();
     end