tidy up mac stack

examples/nexys_a7/lut_ram_ether/send_packet.py

@@ -21,7 +21,7 @@ def read_register(addr):
     sniffer.start()
     from time import sleep
     time.sleep(0.1)
-    sendp(pkt, iface=ifc)
+    sendp(pkt, iface=ifc, verbose = 0)
     results = sniffer.stop()
 
     assert len(results) == 1, "Received more packets than expected!"
@@ -44,7 +44,7 @@ def write_register(addr, data):
 
     pkt = pkt / msg
     pkt.load = msg
-    sendp(pkt, iface=ifc)
+    sendp(pkt, iface=ifc, verbose = 0)
 
 def read_batch(addrs):
     pkts = []
@@ -67,7 +67,7 @@ def read_batch(addrs):
     from time import sleep
     time.sleep(0.1)
 
-    sendp(pkts, iface=ifc)
+    sendp(pkts, iface=ifc, verbose = 0)
     sniffer.join()
     results = sniffer.results
 
@@ -100,26 +100,25 @@ def write_batch(addrs, data):
         pkt = pkt / msg
         pkt.load = msg
 
-    sendp(pkts, iface=ifc)
+    sendp(pkts, iface=ifc, verbose = 0)
 
 
 from time import sleep
 if __name__ == "__main__":
-    # for addr in range(64):
-    #     data = addr
-    #     write_register(addr, data)
+    for addr in range(64):
+        data = addr
+        write_register(addr, data)
+        retval = read_register(addr)
+        if retval != addr:
+            print(f"ERROR: sent {data} got {retval}")
 
-    #     retval = read_register(addr)
-    #     if retval != addr:
-    #         print("oops")
+        else:
+            print(f"SUCCESS: sent {data} got {retval}")
 
-    #     else:
-    #         print(f"yay addr: {addr} worked!")
-
-    addrs = [i for i in range(64)]
-    datas = addrs
-    write_batch(addrs, datas)
-    print("done")
-    retvals = read_batch(addrs)
-    print(retvals)
+    # addrs = [i for i in range(64)]
+    # datas = addrs
+    # write_batch(addrs, datas)
+    # print("done")
+    # retvals = read_batch(addrs)
+    # print(retvals)
 

examples/nexys_a7/lut_ram_ether/src/manta.v

@@ -27,7 +27,10 @@ module manta(
     output reg txen,
     output reg [1:0] txd);
 
-    ethernet_rx erx (
+    ethernet_rx # (
+        .FPGA_MAC(48'h69_69_5A_06_54_91),
+        .ETHERTYPE(16'h88_B5)
+    ) erx (
         .clk(clk),
 
         .crsdv(crsdv),
@@ -64,7 +67,11 @@ module manta(
     reg my_lut_ram_btx_rw;
     reg my_lut_ram_btx_valid;
 
-    ethernet_tx etx (
+    ethernet_tx #(
+        .FPGA_MAC(48'h69_69_5A_06_54_91),
+        .HOST_MAC(48'h00_E0_4C_68_1E_0C),
+        .ETHERTYPE(16'h88_B5)
+    ) etx (
         .clk(clk),
 
         .txen(txen),