add working mac tx

examples/nexys_a7/ethernet_logic_analyzer/derp/csv_to_vcd.py

@@ -1,39 +0,0 @@
-from datetime import datetime
-import numpy as np
-from vcd import VCDWriter
-
-vcd_file = open("iladata.vcd", "w")
-data = np.genfromtxt("iladata.csv", delimiter=',', names=True)
-
-# Use the same datetime format that iVerilog uses
-timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y")
-
-with VCDWriter(vcd_file, '10 ns', timestamp, "manta") as writer:
-
-    # each probe has a name, width, and writer associated with it
-    signals = [{
-        "name" : "eth_crsdv",
-        "width" : 1,
-        "data" : [int(str(i).split('.')[0],2) for i in data['eth_crsdv_IBUF']],
-        "var": writer.register_var("manta", "eth_crsdv", "wire", size=1)
-    },
-
-    {
-        "name" : "eth_rxd",
-        "width" : 2,
-        "data" : [int(str(i).split('.')[0],2) for i in data['eth_rxd_IBUF10']],
-        "var": writer.register_var("manta", "eth_rxd", "wire", size=2)
-    },
-
-    ]
-
-    # add the data to each probe in the vcd file
-    for timestamp in range(32768):
-        # add other signals
-        for signal in signals:
-            var = signal["var"]
-            sample = signal["data"][timestamp]
-
-            writer.change(var, timestamp, sample)
-
-vcd_file.close()

examples/nexys_a7/ethernet_logic_analyzer/sim/turbo_bullshit_tb.sv

@@ -1,7 +1,7 @@
 `default_nettype none
 `timescale 1ns/1ps
 
-module comparison_tb();
+module turbo_bullshit_tb();
     logic ethclk;
     logic rst;
 
@@ -54,11 +54,14 @@ module comparison_tb();
     // assign eth_crsdv_debug = eth_crsdv_playback;
     // assign eth_rxd_debug = eth_rxd_playback;
 
-    // assign eth_crsdv_debug = eth_crsdv_pb9k;
+    assign eth_crsdv_debug = eth_crsdv_pb9k;
-    // assign eth_rxd_debug = eth_rxd_pb9k;
+    assign eth_rxd_debug = eth_rxd_pb9k;
 
-    assign eth_crsdv_debug = eth_crsdv_mtx;
+    // assign eth_crsdv_debug = eth_crsdv_mtx;
-    assign eth_rxd_debug = eth_rxd_mtx;
+    // assign eth_rxd_debug = eth_rxd_mtx;
+
+    reg serenity_now;
+    assign serenity_now = (eth_rxd_mtx != eth_rxd_pb9k);
 
     ether_la_playback #(.MEM_FILE("capture.mem")) ether_la_playback_inst (
         .clk(ethclk),
@@ -141,8 +144,8 @@ module comparison_tb();
 
     initial begin
         ethclk = 0;
-        $dumpfile("comparison_tb.vcd");
+        $dumpfile("turbo_bullshit_tb.vcd");
-        $dumpvars(0, comparison_tb);
+        $dumpvars(0, turbo_bullshit_tb);
         rst = 0;
         pb9k_start = 0;
         mtx_start = 0;

examples/nexys_a7/ethernet_logic_analyzer/src/mac_tx.v

@@ -28,7 +28,7 @@ module mac_tx(
 
     localparam PREAMBLE = {7{8'b01010101}};
     localparam SFD = 8'b11010101;
-    parameter  SRC_MAC = 48'h00_00_00_00_00_00;
+    parameter  SRC_MAC = 48'h69_69_69_69_69_69;
     parameter  DST_MAC = 48'hFF_FF_FF_FF_FF_FF;
     parameter  LENGTH = 16'h1234;
     localparam FCS_DATA = 32'b01001110_00010000_01011001_10011010;
@@ -39,7 +39,8 @@ module mac_tx(
     localparam PREPAYLOAD_LEN = (7 + 1 + 6 + 6 + 2) * 4; // in dibits
     // localparam PAYLOAD_LEN = LENGTH * 4;
     localparam PAYLOAD_LEN = 2 * 4;
-    localparam ZERO_PAD_LEN = (46 * 4) - PAYLOAD_LEN ; // minimum payload size is 46 bytes
+    // localparam ZERO_PAD_LEN = (46 * 4) - PAYLOAD_LEN ; // minimum payload size is 46 bytes
+    localparam ZERO_PAD_LEN = (46 * 4) - PAYLOAD_LEN + 6; // minimum payload size is 46 bytes
     localparam FCS_LEN = 4*4;
     localparam IPG_LEN = 96/2;
 
@@ -62,18 +63,23 @@ module mac_tx(
 
     reg bitorder_axiiv;
     reg [1:0] bitorder_axiid;
+    reg bitorder_axiov;
+    reg [1:0] bitorder_axiod;
 
     bitorder b(
         .clk(clk),
         .rst(rst),
         .axiiv(bitorder_axiiv),
         .axiid(bitorder_axiid),
-        .axiov(txen),
+        .axiov(bitorder_axiov),
-        .axiod(txd));
+        .axiod(bitorder_axiod));
 
     reg crc_axiiv = 0;
     reg crc_axiov;
     reg [31:0] crc_axiod;
+
+    reg [31:0] fcs = 0;
+
     crc32 crc(
         .clk(clk),
         .rst(rst),
@@ -84,6 +90,31 @@ module mac_tx(
         .axiov(crc_axiov),
         .axiod(crc_axiod));
 
+
+    always @(*) begin
+        if (state == FCS && counter == 0) begin
+            txen <= 1;
+            txd <= {crc_axiod[30], crc_axiod[31]};
+        end
+
+        else if (state == FCS && counter != 0) begin
+            txen <= 1;
+            txd <= {fcs[2*(FCS_LEN-counter)-2], fcs[2*(FCS_LEN-counter)-1]};
+        end
+
+        else if (state == IPG) begin
+            txen <= 0;
+            txd <= 0;
+        end
+
+        else begin
+            txen = bitorder_axiov;
+            txd = bitorder_axiod;
+        end
+
+
+    end
+
     always @(posedge clk) begin
 
         // idle state
@@ -126,7 +157,7 @@ module mac_tx(
             bitorder_axiid <= 2'b00;
 
             counter <= counter + 1;
-            if(counter == ZERO_PAD_LEN - 1) begin
+            if(counter == ZERO_PAD_LEN - 2) begin
                 counter <= 0;
                 state <= FCS;
             end
@@ -135,8 +166,8 @@ module mac_tx(
 
         // readout fcs from the checksum module
         else if (state == FCS) begin
-            bitorder_axiiv <= 1;
+
-            bitorder_axiid <= FCS_DATA[2*(FCS_LEN-counter)-1-:2];
+            if(counter == 0) fcs <= crc_axiod;
 
             counter <= counter + 1;
             if(counter == FCS_LEN - 1) begin