pass Ethernet config to LiteEth core generator
This commit is contained in:
Fischer Moseley
parent
63e912fb63
commit
5e642101ef
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@ -192,38 +192,45 @@ class EthernetInterface(Elaboratable):
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sock.sendto(bytes_out, (self.fpga_ip_addr, self.udp_port))
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def generate_liteeth_core(self):
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"""
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Generate a LiteEth core by calling a slightly modified form of the LiteEth
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standalone core generator. This passes the contents of the 'ethernet' section
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of the Manta configuration file to LiteEth, after modifying it slightly to
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include the UDP ports and set a MAC address if the user didn't specify one.
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"""
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liteeth_config = self.config.copy()
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# Randomly assign a MAC address if one is not specified in the configuration.
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# This will choose a MAC address in the Locally Administered, Administratively Assigned group.
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# For more information, see:
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# https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses
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if "mac_address" not in self.config:
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mac_address = list(f"{randint(0, (2**48) - 1):012x}")
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mac_address[1] = "2"
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mac_address = int("".join(mac_address), 16)
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if "mac_address" not in liteeth_config:
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addr = list(f"{randint(0, (2**48) - 1):012x}")
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addr[1] = "2"
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liteeth_config["mac_address"] = int("".join(addr), 16)
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else:
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mac_address = self.config["mac_address"]
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# Force use of DHCP
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liteeth_config["dhcp"] = True
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liteeth_config = {
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"phy": self.config["phy"],
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"vendor": self.config["vendor"],
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"toolchain": self.config["toolchain"],
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"refclk_freq": self.config["refclk_freq"],
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"clk_freq": self.config["clk_freq"],
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"mac_address": mac_address,
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"dhcp": True,
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"data_width": 32,
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"udp_ports": {
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"udp0": {
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"udp_port": self.udp_port,
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"data_width": 32,
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"tx_fifo_depth": 64,
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"rx_fifo_depth": 64,
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}
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},
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# Use UDP
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liteeth_config["core"] = "udp"
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# Use 32-bit words. Might be redundant, as I think using DHCP forces
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# LiteEth to use 32-bit words
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liteeth_config["data_width"] = 32
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# Add UDP port
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liteeth_config["udp_ports"] = {
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"udp0": {
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"udp_port": self.udp_port,
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"data_width": 32,
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"tx_fifo_depth": 64,
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"rx_fifo_depth": 64,
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}
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}
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# Generate the core
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from .liteeth_gen import main
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return main(liteeth_config)
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@ -230,6 +230,8 @@ def get_udp_raw_port_ios(name, data_width):
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# PHY Core -----------------------------------------------------------------------------------------
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class PHYCore(SoCMini):
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SoCMini.csr_map = {
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"ctrl": 0,
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@ -322,8 +324,14 @@ class PHYCore(SoCMini):
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qpll_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45={125e6: 5, 156.25e6: 4}[refclk_freq],
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fbdiv={
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liteeth_phys.A7_1000BASEX: 4,
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liteeth_phys.A7_2500BASEX: 5,
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}[phy],
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fbdiv_45={
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125e6: 5,
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156.25e6: 4,
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}[refclk_freq],
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refclk_div=1,
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)
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qpll = QPLL(ethphy_pads.refclk, qpll_settings)
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@ -371,7 +379,73 @@ class PHYCore(SoCMini):
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)
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# MAC Core -----------------------------------------------------------------------------------------
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class MACCore(PHYCore):
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def __init__(self, platform, core_config):
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# Parameters -------------------------------------------------------------------------------
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nrxslots = core_config.get("nrxslots", 2)
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ntxslots = core_config.get("ntxslots", 2)
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bus_standard = core_config["core"]
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tx_cdc_depth = core_config.get("tx_cdc_depth", 32)
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tx_cdc_buffered = core_config.get("tx_cdc_buffered", False)
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rx_cdc_depth = core_config.get("rx_cdc_depth", 32)
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rx_cdc_buffered = core_config.get("rx_cdc_buffered", False)
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assert bus_standard in ["wishbone", "axi-lite"]
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# PHY --------------------------------------------------------------------------------------
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PHYCore.__init__(self, platform, core_config)
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# MAC --------------------------------------------------------------------------------------
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self.ethmac = ethmac = LiteEthMAC(
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phy=self.ethphy,
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dw=32,
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interface="wishbone",
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endianness=core_config["endianness"],
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nrxslots=nrxslots,
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ntxslots=ntxslots,
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full_memory_we=core_config.get("full_memory_we", False),
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tx_cdc_depth=tx_cdc_depth,
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tx_cdc_buffered=tx_cdc_buffered,
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rx_cdc_depth=rx_cdc_depth,
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rx_cdc_buffered=rx_cdc_buffered,
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)
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if bus_standard == "wishbone":
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# Wishbone Interface -----------------------------------------------------------------------
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wb_bus = wishbone.Interface()
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platform.add_extension(wb_bus.get_ios("wishbone"))
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self.comb += wb_bus.connect_to_pads(
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self.platform.request("wishbone"), mode="slave"
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)
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self.bus.add_master(master=wb_bus)
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if bus_standard == "axi-lite":
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# AXI-Lite Interface -----------------------------------------------------------------------
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axil_bus = axi.AXILiteInterface(address_width=32, data_width=32)
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platform.add_extension(axil_bus.get_ios("bus"))
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self.submodules += axi.Wishbone2AXILite(ethmac.bus, axil_bus)
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self.comb += axil_bus.connect_to_pads(
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self.platform.request("bus"), mode="slave"
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)
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self.bus.add_master(master=axil_bus)
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ethmac_region_size = (nrxslots + ntxslots) * buffer_depth
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ethmac_region = SoCRegion(
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origin=self.mem_map.get("ethmac", None),
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size=ethmac_region_size,
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cached=False,
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)
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self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
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# Interrupt Interface ----------------------------------------------------------------------
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self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)
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# UDP Core -----------------------------------------------------------------------------------------
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class UDPCore(PHYCore):
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def add_streamer_port(self, platform, name, port_cfg):
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# Use default Data-Width of 8-bit when not specified.
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@ -571,6 +645,8 @@ class UDPCore(PHYCore):
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# Build --------------------------------------------------------------------------------------------
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def main(core_config):
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# Convert YAML elements to Python/LiteX --------------------------------------------------------
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for k, v in core_config.items():
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@ -598,7 +674,12 @@ def main(core_config):
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raise ValueError("Unsupported vendor: {}".format(core_config["vendor"]))
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platform.add_extension(_io)
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soc = UDPCore(platform, core_config)
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if core_config["core"] in ["wishbone", "axi-lite"]:
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soc = MACCore(platform, core_config)
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elif core_config["core"] == "udp":
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soc = UDPCore(platform, core_config)
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else:
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raise ValueError("Unknown core: {}".format(core_config["core"]))
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with TemporaryDirectory() as path:
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builder = Builder(soc, compile_gateware=False, output_dir=path)
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