ethernet: send write reponses, fix write request addressing bug
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ff8d6a9e10
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@ -27,8 +27,13 @@ class EthernetBridge(Elaboratable):
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with m.FSM(init="IDLE"):
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with m.State("IDLE"):
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m.d.sync += self.ready_o.eq(1)
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m.d.sync += self.valid_o.eq(0)
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with m.If(self.valid_i):
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# TODO: not necessary, but makes debugging way easier
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m.d.sync += self.last_o.eq(0)
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m.d.sync += self.data_o.eq(0)
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with m.If(self.valid_i & self.ready_o):
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# First 32 bits was presented, which contains message type (first 3 bits)
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# as well as sequence number (next 13 bits). The remaining 16 bits are unused.
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@ -70,7 +75,6 @@ class EthernetBridge(Elaboratable):
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m.next = "READ_WAIT_FOR_ADDR"
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with m.Elif(self.data_i[:3] == MessageTypes.WRITE_REQUEST):
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m.d.sync += seq_num_expected.eq(seq_num_expected + 1)
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m.next = "WRITE_WAIT_FOR_ADDR"
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with m.State("READ_WAIT_FOR_ADDR"):
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@ -140,22 +144,31 @@ class EthernetBridge(Elaboratable):
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m.next = "WRITE"
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with m.State("WRITE"):
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with m.If(self.valid_i):
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m.d.sync += self.bus_o.addr.eq(self.bus_i.addr + 1)
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with m.If(self.valid_i & self.ready_o):
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m.d.sync += self.bus_o.addr.eq(self.bus_o.addr + 1)
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m.d.sync += self.bus_o.data.eq(self.data_i)
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m.d.sync += self.bus_o.rw.eq(1)
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m.d.sync += self.bus_o.valid.eq(1)
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m.d.sync += self.bus_o.last.eq(self.last_i)
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with m.If(self.last_i):
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m.d.sync += self.ready_o.eq(0)
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with m.Else():
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m.d.sync += self.bus_o.eq(0)
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with m.If(self.bus_o.last):
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m.d.sync += self.bus_o.valid.eq(0)
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m.d.sync += self.bus_o.addr.eq(0)
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m.d.sync += self.bus_o.data.eq(0)
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m.d.sync += self.bus_o.last.eq(0)
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m.d.sync += self.bus_o.rw.eq(0)
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with m.If(self.bus_i.last):
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m.d.sync += seq_num_expected.eq(seq_num_expected + 1)
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m.d.sync += self.data_o.eq(
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Cat(
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C(0, unsigned(16)),
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seq_num_expected,
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MessageTypes.WRITE_RESPONSE,
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)
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)
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m.d.sync += self.valid_o.eq(1)
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m.d.sync += self.last_o.eq(1)
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m.next = "IDLE" # TODO: could save a cycle by checking valid_i to see if there's more work to do
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with m.Else():
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