logic_analyzer: use context manager for VCD file export
This commit is contained in:
parent
8aeef78ec6
commit
35c981c4f2
|
|
@ -129,9 +129,11 @@ class LogicAnalyzerCapture:
|
||||||
|
|
||||||
# Use the same datetime format that iVerilog uses
|
# Use the same datetime format that iVerilog uses
|
||||||
timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y")
|
timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y")
|
||||||
vcd_file = open(path, "w")
|
|
||||||
|
|
||||||
with VCDWriter(vcd_file, timescale, timestamp, "manta") as writer:
|
with (
|
||||||
|
open(path, "w") as vcd_file,
|
||||||
|
VCDWriter(vcd_file, timescale, timestamp, "manta") as writer,
|
||||||
|
):
|
||||||
# Each probe has a name, width, and writer associated with it
|
# Each probe has a name, width, and writer associated with it
|
||||||
signals = []
|
signals = []
|
||||||
for p in self._probes:
|
for p in self._probes:
|
||||||
|
|
@ -168,8 +170,6 @@ class LogicAnalyzerCapture:
|
||||||
|
|
||||||
writer.change(var, sample_timestamp, sample)
|
writer.change(var, sample_timestamp, sample)
|
||||||
|
|
||||||
vcd_file.close()
|
|
||||||
|
|
||||||
def get_playback_module(self):
|
def get_playback_module(self):
|
||||||
"""
|
"""
|
||||||
Returns an Amaranth module that will playback the captured data. This
|
Returns an Amaranth module that will playback the captured data. This
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue