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tests: add ethernet_io_core to build_examples test

This commit is contained in:
Fischer Moseley 2024-11-24 16:22:32 -08:00
parent 56e9ed85e5
commit 2761507803
1 changed files with 3 additions and 1 deletions
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4
test/test_examples_build.py
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@ -28,14 +28,15 @@ def test_verilog_examples_build(root_dir):
parent_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), "..")) parent_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
sys.path.insert(0, parent_dir) sys.path.insert(0, parent_dir)
# Import Examples
# Import Platforms # Import Platforms
from amaranth_boards.icestick import ICEStickPlatform from amaranth_boards.icestick import ICEStickPlatform
from amaranth_boards.nexys4ddr import Nexys4DDRPlatform from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
# Import Examples
from examples.amaranth.uart_io_core import UARTIOCoreExample from examples.amaranth.uart_io_core import UARTIOCoreExample
from examples.amaranth.uart_logic_analyzer import UARTLogicAnalyzerExample from examples.amaranth.uart_logic_analyzer import UARTLogicAnalyzerExample
from examples.amaranth.uart_memory_core import UARTMemoryCoreExample from examples.amaranth.uart_memory_core import UARTMemoryCoreExample
from examples.amaranth.ethernet_io_core import EthernetIOCoreExample
# Manually specify a list of examples/platforms to test. # Manually specify a list of examples/platforms to test.
@ -49,6 +50,7 @@ amaranth_examples_cases = [
(UARTLogicAnalyzerExample, ICEStickPlatform), (UARTLogicAnalyzerExample, ICEStickPlatform),
(UARTLogicAnalyzerExample, Nexys4DDRPlatform), (UARTLogicAnalyzerExample, Nexys4DDRPlatform),
(UARTMemoryCoreExample, Nexys4DDRPlatform), (UARTMemoryCoreExample, Nexys4DDRPlatform),
(EthernetIOCoreExample, Nexys4DDRPlatform),
] ]