banish relative imports

src/manta/__init__.py

@@ -1,5 +1,5 @@
-from .manta import Manta
-from .cli import main
+from manta.manta import Manta
+from manta.cli import main
 
 if __name__ == "__main__":
     main()

src/manta/__main__.py

@@ -1,3 +1,3 @@
-from .cli import main
+from manta.cli import main
 
 main()

src/manta/cli.py

@@ -1,5 +1,5 @@
-from .manta import Manta
-from .utils import *
+from manta.manta import Manta
+from manta.utils import *
 from sys import argv
 from pkg_resources import get_distribution
 

src/manta/ethernet/__init__.py

@@ -1,7 +1,7 @@
 from amaranth import *
-from ..utils import *
-from .source_bridge import UDPSourceBridge
-from .sink_bridge import UDPSinkBridge
+from manta.utils import *
+from manta.ethernet.source_bridge import UDPSourceBridge
+from manta.ethernet.sink_bridge import UDPSinkBridge
 from random import randint
 import socket
 
@@ -195,10 +195,9 @@ class EthernetInterface(Elaboratable):
         """
         Generate a LiteEth core by calling a slightly modified form of the LiteEth
         standalone core generator. This passes the contents of the 'ethernet' section
-        of the Manta configuration file to LiteEth, after modifying it slightly to
-        include the UDP ports and set a MAC address if the user didn't specify one.
+        of the Manta configuration file to LiteEth, after modifying it slightly.
         """
-        liteeth_config = self.config.copy()
+        liteeth_config = self._config.copy()
 
         # Randomly assign a MAC address if one is not specified in the configuration.
         # This will choose a MAC address in the Locally Administered, Administratively Assigned group.
@@ -231,6 +230,6 @@ class EthernetInterface(Elaboratable):
         }
 
         # Generate the core
-        from .liteeth_gen import main
+        from manta.ethernet.liteeth_gen import main
 
         return main(liteeth_config)

src/manta/io_core.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from .utils import *
+from manta.utils import *
 from math import ceil
 
 

src/manta/logic_analyzer/__init__.py

@@ -1,9 +1,9 @@
 from amaranth import *
-from ..utils import *
-from .trigger_block import LogicAnalyzerTriggerBlock
-from .fsm import LogicAnalyzerFSM, States, TriggerModes
-from .sample_mem import LogicAnalyzerSampleMemory
-from .playback import LogicAnalyzerPlayback
+from manta.utils import *
+from manta.logic_analyzer.trigger_block import LogicAnalyzerTriggerBlock
+from manta.logic_analyzer.fsm import LogicAnalyzerFSM, States, TriggerModes
+from manta.logic_analyzer.sample_mem import LogicAnalyzerSampleMemory
+from manta.logic_analyzer.playback import LogicAnalyzerPlayback
 
 
 class LogicAnalyzerCore(Elaboratable):

src/manta/logic_analyzer/fsm.py

@@ -1,7 +1,7 @@
 from amaranth import *
 from amaranth.lib.enum import IntEnum
 from math import ceil, log2
-from ..io_core import IOCore
+from manta.io_core import IOCore
 
 
 class States(IntEnum):

src/manta/logic_analyzer/sample_mem.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from ..memory_core import ReadOnlyMemoryCore
+from manta.memory_core import ReadOnlyMemoryCore
 
 
 class LogicAnalyzerSampleMemory(ReadOnlyMemoryCore):

src/manta/logic_analyzer/trigger_block.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from ..io_core import IOCore
+from manta.io_core import IOCore
 
 
 class LogicAnalyzerTriggerBlock(Elaboratable):

src/manta/manta.py

@@ -1,10 +1,10 @@
 from amaranth import *
-from .uart import UARTInterface
+from manta.uart import UARTInterface
 
-from .ethernet import EthernetInterface
-from .io_core import IOCore
-from .memory_core import ReadOnlyMemoryCore
-from .logic_analyzer import LogicAnalyzerCore
+from manta.ethernet import EthernetInterface
+from manta.io_core import IOCore
+from manta.memory_core import ReadOnlyMemoryCore
+from manta.logic_analyzer import LogicAnalyzerCore
 
 
 class Manta(Elaboratable):

src/manta/memory_core.py

@@ -1,5 +1,5 @@
 from amaranth import *
-from .utils import *
+from manta.utils import *
 from math import ceil
 
 

src/manta/uart/__init__.py

@@ -1,9 +1,9 @@
 from amaranth import *
-from ..utils import *
-from .receiver import UARTReceiver
-from .receive_bridge import ReceiveBridge
-from .transmitter import UARTTransmitter
-from .transmit_bridge import TransmitBridge
+from manta.utils import *
+from manta.uart.receiver import UARTReceiver
+from manta.uart.receive_bridge import ReceiveBridge
+from manta.uart.transmitter import UARTTransmitter
+from manta.uart.transmit_bridge import TransmitBridge
 from serial import Serial
 
 
@@ -16,11 +16,7 @@ class UARTInterface(Elaboratable):
         self._clocks_per_baud = int(self._clock_freq // self._baudrate)
         self._check_config()
 
-        # Set chunk_size, which is the max amount of bytes that the core will
-        # dump to the OS driver at a time. Since the FPGA will return bytes
-        # almost instantaneously, this prevents the OS's input buffer from
-        # overflowing, and dropping bytes.
-
+        # Top-Level Ports
         self.rx = Signal()
         self.tx = Signal()
 
@@ -139,9 +135,14 @@ class UARTInterface(Elaboratable):
 
         # Make sure all list elements are integers
         if not all(isinstance(a, int) for a in addrs):
-            raise ValueError("Read address must be an integer or list of integers.")
+            raise TypeError("Read address must be an integer or list of integers.")
+
+        # Send read requests in chunks, and read bytes after each.
+        # The input buffer exposed by the OS on most hosts isn't terribly deep,
+        # so sending in chunks (instead of all at once) prevents the OS's input
+        # buffer from overflowing and dropping bytes, as the FPGA will send
+        # responses instantly after it's received a request.
 
-        # Send read requests, and get responses
         ser = self._get_serial_device()
         addr_chunks = split_into_chunks(addrs, self._chunk_size)
         datas = []
@@ -178,15 +179,15 @@ class UARTInterface(Elaboratable):
 
         # Make sure address and datas are all integers
         if not isinstance(addrs, list) or not isinstance(datas, list):
-            raise ValueError(
+            raise TypeError(
                 "Write addresses and data must be an integer or list of integers."
             )
 
         if not all(isinstance(a, int) for a in addrs):
-            raise ValueError("Write addresses must be all be integers.")
+            raise TypeError("Write addresses must be all be integers.")
 
         if not all(isinstance(d, int) for d in datas):
-            raise ValueError("Write data must all be integers.")
+            raise TypeError("Write data must all be integers.")
 
         # Since the FPGA doesn't issue any responses to write requests, we
         # the host's input buffer isn't written to, and we don't need to