wrap docstrings at 80 chars

src/manta/ethernet/__init__.py

@@ -10,8 +10,8 @@ class EthernetInterface(Elaboratable):
     """
     A module for communicating with Manta over Ethernet, using UDP.
 
-    Provides methods for generating synthesizable logic for the FPGA,
-    as well as methods for reading and writing to memory by the host.
+    Provides methods for generating synthesizable logic for the FPGA, as well
+    as methods for reading and writing to memory by the host.
     """
 
     def __init__(self, config):
@@ -84,8 +84,8 @@ class EthernetInterface(Elaboratable):
 
     def get_top_level_ports(self):
         """
-        Return the Amaranth signals that should be included as ports in the top-level
-        Manta module.
+        Return the Amaranth signals that should be included as ports in the
+        top-level Manta module.
         """
         ports = [
             self.rmii_clocks_ref_clk,
@@ -166,8 +166,8 @@ class EthernetInterface(Elaboratable):
 
     def read(self, addrs):
         """
-        Read the data stored in a set of address on Manta's internal memory. Addresses
-        must be specified as either integers or a list of integers.
+        Read the data stored in a set of address on Manta's internal memory.
+        Addresses must be specified as either integers or a list of integers.
         """
 
         # Handle a single integer address
@@ -205,8 +205,9 @@ class EthernetInterface(Elaboratable):
 
     def write(self, addrs, datas):
         """
-        Write the provided data into the provided addresses in Manta's internal memory.
-        Addresses and data must be specified as either integers or a list of integers.
+        Write the provided data into the provided addresses in Manta's internal
+        memory. Addresses and data must be specified as either integers or a
+        list of integers.
         """
 
         # Handle a single integer address and data
@@ -241,9 +242,10 @@ class EthernetInterface(Elaboratable):
 
     def generate_liteeth_core(self):
         """
-        Generate a LiteEth core by calling a slightly modified form of the LiteEth
-        standalone core generator. This passes the contents of the 'ethernet' section
-        of the Manta configuration file to LiteEth, after modifying it slightly.
+        Generate a LiteEth core by calling a slightly modified form of the
+        LiteEth standalone core generator. This passes the contents of the
+        'ethernet' section of the Manta configuration file to LiteEth, after
+        modifying it slightly.
         """
         liteeth_config = self._config.copy()
 

src/manta/ethernet/sink_bridge.py

@@ -4,10 +4,8 @@ from manta.utils import *
 
 class UDPSinkBridge(Elaboratable):
     """
-    A module for bridging Manta's internal bus to an AXI stream of UDP
-    packet data.
-
-    Connects to the LiteEth core's "sink" port.
+    A module for bridging Manta's internal bus to an AXI stream of UDP packet
+    data. Connects to the LiteEth core's "sink" port.
     """
 
     def __init__(self):

src/manta/ethernet/source_bridge.py

@@ -4,10 +4,8 @@ from manta.utils import *
 
 class UDPSourceBridge(Elaboratable):
     """
-    A module for bridging the AXI-stream of incoming UDP packet data to
-    Manta's internal bus.
-
-    Connects to the LiteEth core's "source" port.
+    A module for bridging the AXI-stream of incoming UDP packet data to Manta's
+    internal bus. Connects to the LiteEth core's "source" port.
     """
 
     def __init__(self):

src/manta/logic_analyzer/__init__.py

@@ -7,7 +7,8 @@ from manta.logic_analyzer.playback import LogicAnalyzerPlayback
 
 
 class LogicAnalyzerCore(Elaboratable):
-    """A logic analzyer, implemented in the FPGA fabric. Connects to the rest of the cores
+    """
+    A logic analzyer, implemented in the FPGA fabric. Connects to the rest of the cores
     over Manta's internal bus, and may be operated from a user's machine through the Python API.
 
     Parameters:

src/manta/logic_analyzer/playback.py

@@ -2,16 +2,11 @@ from amaranth import *
 
 
 class LogicAnalyzerPlayback(Elaboratable):
-    """A synthesizable module that plays back data captured by a LogicAnalyzerCore.
+    """
+    A synthesizable module that plays back data captured by a LogicAnalyzerCore.
 
-    Parameters:
-    ----------
-    data : list[int]
-        The raw captured data taken by the LogicAnalyzerCore. This consists of the values of
-        all the input probes concatenated together at every timestep.
-
-    config : dict
-        The configuration of the LogicAnalyzerCore that took this capture.
+    Takes a list of all the samples captured by a core, along with the config
+    of the core used to take it.
     """
 
     def __init__(self, data, config):

src/manta/logic_analyzer/sample_mem.py

@@ -3,6 +3,11 @@ from manta.memory_core import ReadOnlyMemoryCore
 
 
 class LogicAnalyzerSampleMemory(ReadOnlyMemoryCore):
+    """
+    A module that wraps a ReadOnlyMemoryCore, using the config from a LogicAnalyzerCore
+    to determine the parameters with which to instantiate the core.
+    """
+
     def __init__(self, config, base_addr, interface):
         width = sum(config["probes"].values())
         depth = config["sample_depth"]

src/manta/uart/__init__.py

@@ -11,8 +11,8 @@ class UARTInterface(Elaboratable):
     """
     A module for communicating with Manta over UART.
 
-    Provides methods for generating synthesizable logic for the FPGA,
-    as well as methods for reading and writing to memory by the host.
+    Provides methods for generating synthesizable logic for the FPGA, as well
+    as methods for reading and writing to memory by the host.
     """
 
     def __init__(self, port, baudrate, clock_freq, chunk_size=256):
@@ -80,7 +80,8 @@ class UARTInterface(Elaboratable):
 
     def _get_serial_device(self):
         """
-        Return an open PySerial serial device if one exists, otherwise, open one and return it.
+        Return an open PySerial serial device if one exists, otherwise, open
+        one and return it.
         """
 
         # Check if we've already opened a device
@@ -129,15 +130,15 @@ class UARTInterface(Elaboratable):
 
     def get_top_level_ports(self):
         """
-        Return the Amaranth signals that should be included as ports in the top-level
-        Manta module.
+        Return the Amaranth signals that should be included as ports in the
+        top-level Manta module.
         """
         return [self.rx, self.tx]
 
     def read(self, addrs):
         """
-        Read the data stored in a set of address on Manta's internal memory. Addresses
-        must be specified as either integers or a list of integers.
+        Read the data stored in a set of address on Manta's internal memory.
+        Addresses must be specified as either integers or a list of integers.
         """
 
         # Handle a single integer address
@@ -180,8 +181,9 @@ class UARTInterface(Elaboratable):
 
     def write(self, addrs, datas):
         """
-        Write the provided data into the provided addresses in Manta's internal memory.
-        Addresses and data must be specified as either integers or a list of integers.
+        Write the provided data into the provided addresses in Manta's internal
+        memory. Addresses and data must be specified as either integers or a
+        list of integers.
         """
 
         # Handle a single integer address and data
@@ -212,7 +214,8 @@ class UARTInterface(Elaboratable):
 
     def _decode_read_response(self, response_bytes):
         """
-        Check that read response is formatted properly, and return the encoded data if so.
+        Check that read response is formatted properly, and return the encoded
+        data if so.
         """
 
         # Make sure response is not empty

src/manta/uart/receive_bridge.py

@@ -11,8 +11,8 @@ class States(IntEnum):
 
 class ReceiveBridge(Elaboratable):
     """
-    A module for bridging the stream of bytes from the UARTReceiver
-    module to Manta's internal bus.
+    A module for bridging the stream of bytes from the UARTReceiver module to
+    Manta's internal bus.
     """
 
     def __init__(self):

src/manta/uart/receiver.py

@@ -3,8 +3,8 @@ from amaranth import *
 
 class UARTReceiver(Elaboratable):
     """
-    A module for receiving bytes on a 8N1 UART at a configurable
-    baudrate. Outputs bytes as a stream.
+    A module for receiving bytes on a 8N1 UART at a configurable baudrate.
+    Outputs bytes as a stream.
     """
 
     def __init__(self, clocks_per_baud):

src/manta/uart/transmit_bridge.py

@@ -3,8 +3,8 @@ from amaranth import *
 
 class TransmitBridge(Elaboratable):
     """
-    A module for bridging Manta's internal bus to the stream of bytes
-    expected by the UARTTransmitter module.
+    A module for bridging Manta's internal bus to the stream of bytes expected
+    by the UARTTransmitter module.
     """
 
     def __init__(self):

src/manta/uart/transmitter.py

@@ -3,8 +3,8 @@ from amaranth import *
 
 class UARTTransmitter(Elaboratable):
     """
-    A module for transmitting bytes on a 8N1 UART at a configurable
-    baudrate. Accepts bytes as a stream.
+    A module for transmitting bytes on a 8N1 UART at a configurable baudrate.
+    Accepts bytes as a stream.
     """
 
     def __init__(self, clocks_per_baud):