luke
/
manta
mirror of https://github.com/fischermoseley/manta.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

move back to iverilog 13 compatability

This commit is contained in:
Fischer Moseley 2023-04-16 15:59:18 -04:00
parent ca814df63e
commit 07624d83ee
1 changed files with 2 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
View File

@ -50,10 +50,8 @@ task write_and_verify(
assert(read_data == write_data) else $error("data read does not match data written!"); assert(read_data == write_data) else $error("data read does not match data written!");
endtask endtask
task read_all_reg( task read_all_reg();
string desc string desc;
);
for(int i = 0; i < (logic_analyzer_tb.la.block_mem.MAX_ADDR); i++) begin for(int i = 0; i < (logic_analyzer_tb.la.block_mem.MAX_ADDR); i++) begin
if(i == logic_analyzer_tb.la.fsm_registers.BASE_ADDR) desc = "FSM"; if(i == logic_analyzer_tb.la.fsm_registers.BASE_ADDR) desc = "FSM";