uart: rewrite bridge to support backpressure on output
This commit is contained in:
Fischer Moseley
parent
de42bf98f4
commit
018f7cc223
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@ -15,183 +15,138 @@ class EthernetBridge(wiring.Component):
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def elaborate(self, platform):
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def elaborate(self, platform):
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m = Module()
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m = Module()
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msg_type = Signal(MessageTypes)
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seq_num_expected = Signal(13)
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seq_num_expected = Signal(13)
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read_len = Signal(7)
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with m.FSM(init="IDLE"):
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seen_last = Signal()
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count = Signal(7)
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with m.FSM() as fsm:
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with m.State("IDLE"):
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with m.State("IDLE"):
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m.d.sync += self.sink.ready.eq(1)
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m.d.sync += self.source.valid.eq(0)
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# TODO: not necessary, but makes debugging way easier
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m.d.sync += self.source.last.eq(0)
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m.d.sync += self.source.data.eq(0)
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with m.If(self.sink.valid & self.sink.ready):
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with m.If(self.sink.valid & self.sink.ready):
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# First 32 bits was presented, which contains message type (first 3 bits)
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# as well as sequence number (next 13 bits). The remaining 16 bits are unused.
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# Send NACK if message type or sequence number is incorrect
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# Send NACK if message type or sequence number is incorrect
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with m.If(
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with m.If(
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(self.sink.data[:3] > max(MessageTypes))
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(
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(self.sink.data[:3] != MessageTypes.READ_REQUEST)
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& (self.sink.data[:3] != MessageTypes.WRITE_REQUEST)
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)
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| (self.sink.data[3:16] != seq_num_expected)
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| (self.sink.data[3:16] != seq_num_expected)
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):
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):
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# Wait to NACK if this isn't the last beat in message
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m.d.sync += seen_last.eq(self.sink.last)
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with m.If(~self.sink.last):
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m.next = "NACK"
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m.next = "NACK_WAIT_FOR_LAST"
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# Otherwise, NACK immediately
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with m.Else():
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with m.Else():
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m.d.sync += msg_type.eq(self.sink.data[:3])
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m.d.sync += self.source.data.eq(
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m.d.sync += count.eq(self.sink.data[16:23])
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EthernetMessageHeader.concat_signals(
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m.next = "WAIT_FOR_ADDR"
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MessageTypes.NACK,
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seq_num_expected,
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)
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)
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m.d.sync += self.source.valid.eq(1)
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m.d.sync += self.source.last.eq(1)
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m.d.sync += self.sink.ready.eq(0)
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m.next = "NACK_WAIT_FOR_READY"
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with m.Elif(self.sink.data[:3] == MessageTypes.READ_REQUEST):
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with m.State("WAIT_FOR_ADDR"):
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m.d.sync += seq_num_expected.eq(seq_num_expected + 1)
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with m.If(self.sink.valid & self.sink.ready):
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m.d.sync += read_len.eq(self.sink.data[16:23] - 1)
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m.d.sync += self.bus_source.p.addr.eq(self.sink.data)
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m.d.sync += seq_num_expected.eq(seq_num_expected + 1)
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with m.If(msg_type == MessageTypes.READ_REQUEST):
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# Send read response header
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m.d.sync += self.source.valid.eq(1)
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m.d.sync += self.source.last.eq(0)
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m.d.sync += self.source.data.eq(
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m.d.sync += self.source.data.eq(
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EthernetMessageHeader.concat_signals(
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EthernetMessageHeader.concat_signals(
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MessageTypes.READ_RESPONSE,
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MessageTypes.READ_RESPONSE,
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seq_num_expected,
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seq_num_expected,
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)
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)
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)
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)
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m.d.sync += self.source.valid.eq(1)
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m.next = "READ_WAIT_FOR_ADDR"
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with m.Elif(self.sink.data[:3] == MessageTypes.WRITE_REQUEST):
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m.next = "READ"
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m.next = "WRITE_WAIT_FOR_ADDR"
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with m.State("READ_WAIT_FOR_ADDR"):
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with m.Elif(msg_type == MessageTypes.WRITE_REQUEST):
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m.d.sync += self.source.valid.eq(0)
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m.d.sync += self.source.data.eq(0)
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with m.If(self.sink.valid):
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# we have the length and the address to read from, let's go!
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m.d.sync += self.bus_source.p.addr.eq(self.sink.data)
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m.d.sync += self.bus_source.p.data.eq(0)
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m.d.sync += self.bus_source.p.rw.eq(0)
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m.d.sync += self.bus_source.p.valid.eq(1)
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with m.If(read_len == 0):
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# we've sent the last read request in this batch to the bus
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m.d.sync += self.bus_source.p.last.eq(1)
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m.d.sync += read_len.eq(0)
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m.next = "READ"
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with m.State("READ"):
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m.d.sync += self.sink.ready.eq(0)
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# Clock out read requests to the bus
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with m.If(read_len > 0):
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m.d.sync += self.bus_source.p.addr.eq(self.bus_source.p.addr + 1)
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m.d.sync += read_len.eq(read_len - 1)
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with m.If(read_len == 1):
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m.d.sync += self.bus_source.p.last.eq(1)
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with m.Else():
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m.d.sync += self.bus_source.p.eq(
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0
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) # TODO: it's probably overzealous to set the whole bus to zero, but it makes debugging easy so we're doing it xD
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# Clock out any read data from the bus
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with m.If(self.bus_sink.p.valid):
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m.d.sync += self.source.data.eq(self.bus_sink.p.data)
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m.d.sync += self.source.valid.eq(1)
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m.d.sync += self.source.last.eq(self.bus_sink.p.last)
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with m.If(self.source.last):
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m.d.sync += self.source.data.eq(0)
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m.d.sync += self.source.valid.eq(0)
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m.d.sync += self.source.last.eq(0)
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m.next = "IDLE" # TODO: could save a cycle by checking valid_i to see if there's more work to do
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with m.State("WRITE_WAIT_FOR_ADDR"):
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with m.If(self.sink.valid):
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m.d.sync += self.bus_source.p.addr.eq(self.sink.data)
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m.next = "WRITE_FIRST"
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# Don't want to increment address on the first write,
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# and I'm lazy so I'm making a new state to keep track of that
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with m.State("WRITE_FIRST"):
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with m.If(self.sink.valid):
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m.d.sync += self.bus_source.p.data.eq(self.sink.data)
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m.d.sync += self.bus_source.p.rw.eq(1)
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m.d.sync += self.bus_source.p.valid.eq(1)
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m.d.sync += self.bus_source.p.last.eq(self.sink.last)
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with m.If(self.sink.last):
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m.d.sync += self.sink.ready.eq(0)
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m.next = "WRITE_WAIT_FOR_LAST"
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with m.Else():
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m.next = "WRITE"
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m.next = "WRITE"
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with m.State("WRITE"):
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with m.State("WRITE"):
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with m.If(self.sink.valid):
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# Keep a running count of the number of requests inflight on the bus
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# Once that hits zero and seen_last is high, we're done!
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# Send write response and wait for it to clock out
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m.d.sync += seen_last.eq(
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seen_last | (self.sink.last & self.sink.valid & self.sink.ready)
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)
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m.d.sync += count.eq(
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count + (self.sink.valid & self.sink.ready) - self.bus_sink.p.valid
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)
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with m.If(self.sink.valid & self.sink.ready):
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m.d.sync += self.bus_source.p.addr.eq(self.bus_source.p.addr + 1)
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m.d.sync += self.bus_source.p.addr.eq(self.bus_source.p.addr + 1)
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m.d.sync += self.bus_source.p.data.eq(self.sink.data)
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m.d.sync += self.bus_source.p.data.eq(self.sink.data)
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m.d.sync += self.bus_source.p.rw.eq(1)
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m.d.sync += self.bus_source.p.rw.eq(1)
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m.d.sync += self.bus_source.p.valid.eq(1)
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m.d.sync += self.bus_source.p.valid.eq(1)
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m.d.sync += self.bus_source.p.last.eq(self.sink.last)
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with m.If(self.sink.last):
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m.d.sync += self.sink.ready.eq(0)
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m.next = "WRITE_WAIT_FOR_LAST"
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with m.Else():
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m.next = "WRITE"
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with m.Else():
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with m.Else():
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m.next = "WRITE"
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m.d.sync += self.bus_source.p.data.eq(0) # just for clarity of debugging
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m.d.sync += self.bus_source.p.rw.eq(0) # just for clarity of debugging
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m.d.sync += self.bus_source.p.valid.eq(0)
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with m.State("WRITE_WAIT_FOR_LAST"):
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with m.If(seen_last & (count == 0)):
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m.d.sync += self.bus_source.p.eq(0)
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with m.If(self.source.valid & self.source.ready):
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m.d.sync += self.source.valid.eq(0)
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m.d.sync += self.source.last.eq(0) # just for clarity of debugging
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m.d.sync += self.source.data.eq(0) # just for clarity of debugging
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m.next = "IDLE"
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with m.If(self.bus_sink.p.last):
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with m.Else():
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m.d.sync += seq_num_expected.eq(seq_num_expected + 1)
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m.d.sync += self.source.valid.eq(1)
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m.d.sync += self.source.data.eq(
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m.d.sync += self.source.last.eq(1)
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EthernetMessageHeader.concat_signals(
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m.d.sync += self.source.data.eq(
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MessageTypes.WRITE_RESPONSE,
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EthernetMessageHeader.concat_signals(
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seq_num_expected,
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MessageTypes.WRITE_RESPONSE,
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seq_num_expected,
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)
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)
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)
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)
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with m.State("READ"):
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# Wait for downstream to accept data. Put next read request on the bus after it's accepted, if more is needed
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m.d.sync += self.bus_source.p.valid.eq(0)
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with m.If(self.source.valid):
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with m.If(self.source.ready):
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m.d.sync += self.source.valid.eq(0)
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m.d.sync += self.source.data.eq(0) # for debugging
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m.d.sync += self.source.last.eq(0) # for debugging
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with m.If(self.source.last):
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m.next = "IDLE"
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with m.Else():
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m.d.sync += self.bus_source.p.rw.eq(0)
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m.d.sync += self.bus_source.p.valid.eq(1)
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m.d.sync += count.eq(count - 1)
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# Not waiting on downstream to accept data. No need to issue bus request.
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# Instead check if data's available on bus_sink, and put it on source if so
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with m.Else():
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with m.If(self.bus_sink.p.valid):
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m.d.sync += self.source.data.eq(self.bus_sink.p.data)
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m.d.sync += self.source.valid.eq(1)
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m.d.sync += self.source.last.eq(count == 0)
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m.d.sync += self.bus_source.p.addr.eq(self.bus_source.p.addr + 1)
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with m.State("NACK"):
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# Only send NACK after full packet has been received
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with m.If(seen_last | (self.sink.valid & self.sink.ready & self.sink.last)):
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m.d.sync += self.source.valid.eq(1)
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m.d.sync += self.source.valid.eq(1)
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m.d.sync += self.source.last.eq(1)
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m.d.sync += self.source.last.eq(1)
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m.next = "IDLE" # TODO: could save a cycle by checking valid_i to see if there's more work to do
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with m.State("NACK_WAIT_FOR_LAST"):
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with m.If(self.sink.last):
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m.d.sync += self.source.data.eq(
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m.d.sync += self.source.data.eq(
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EthernetMessageHeader.concat_signals(
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EthernetMessageHeader.concat_signals(
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MessageTypes.NACK,
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MessageTypes.NACK,
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seq_num_expected,
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seq_num_expected,
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)
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)
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)
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)
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m.d.sync += self.source.valid.eq(1)
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m.d.sync += self.source.last.eq(1)
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m.d.sync += self.sink.ready.eq(0)
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m.next = "NACK_WAIT_FOR_READY"
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with m.State("NACK_WAIT_FOR_READY"):
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with m.If(self.source.ready):
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m.d.sync += self.source.valid.eq(0)
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# TODO: remove these next two lines, they're not necessary
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# although they are nice for debug...
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m.d.sync += self.source.data.eq(0)
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m.d.sync += self.source.last.eq(0)
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m.d.sync += self.sink.ready.eq(1)
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with m.If(self.source.valid & self.source.ready):
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m.next = "IDLE"
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m.next = "IDLE"
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m.d.sync += self.source.valid.eq(0)
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m.d.sync += self.source.last.eq(0)
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m.d.sync += self.source.data.eq(0)
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m.d.comb += self.sink.ready.eq(~fsm.ongoing("READ"))
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return m
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return m
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