manta/test/test_mem_core_sim.py

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2023-12-28 23:22:29 +01:00
from manta.memory_core import ReadOnlyMemoryCore
from manta.utils import *
from random import randint, sample
def fill_mem_from_user_port(mem_core, depth):
for i in range(depth):
yield mem_core.user_addr.eq(i)
yield mem_core.user_data.eq(i)
yield mem_core.user_we.eq(1)
yield
yield mem_core.user_we.eq(0)
yield
def verify_mem_core(width, depth, base_addr):
config = {"type": "memory", "width": width, "depth": depth}
mem_core = ReadOnlyMemoryCore(config, base_addr, interface=None)
def testbench():
yield from fill_mem_from_user_port(mem_core, depth)
# Read from address sequentially
for i in range(depth):
yield from verify_register(mem_core, i + base_addr, i % (2**width))
# Read from addresses randomly
for i in sample(range(depth), k=depth):
yield from verify_register(mem_core, i + base_addr, i % (2**width))
simulate(mem_core, testbench)
def test_sweep_core_widths():
for i in range(1, 64):
verify_mem_core(i, 128, 0)
def test_random_cores():
for _ in range(5):
width = randint(0, 512)
depth = randint(0, 1024)
base_addr = randint(0, 2**16 - 1 - depth)
verify_mem_core(width, depth, base_addr)