2023-07-20 04:27:12 +02:00
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# Roadmap
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## Prior to v1.0.0 release:
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_targeting August 2023_
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2023-07-24 18:03:46 +02:00
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2023-08-16 08:07:59 +02:00
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- ~~Clean up UART testbenches, make them actually test things~~
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2023-07-20 04:27:12 +02:00
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- Pull text from thesis into documentation site
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2023-08-16 08:07:59 +02:00
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- Add API reference to documentation site
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2023-07-20 04:27:12 +02:00
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- Port logic analyzer examples to the icestick
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2023-08-16 08:07:59 +02:00
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- This requires refactoring the block memory core to use unpacked arrays, since Yosys doesn't support packed arrays.
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- Add method for dumping logic analyzer data to Python
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- Add clock domain crossing to IO core
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- Verify that >16 bit probes work on IO core
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- Add clock domain crossing to Logic Analyzer Core
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- Verify that capture modes work on the Logic Analyzer Core
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- Verify that external triggers work on the Logic Analyzer Core
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- Add global AND/OR to Logic Analyzer Core
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- Make super super sure everything works (need hardware for that)
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2023-07-20 04:27:12 +02:00
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## Prior to v1.1.0 release:
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- Fix Ethernet packet format
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- Switch from Scapy to Python sockets library
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## Prior to v1.2.0 release:
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- [FuseSoC](https://github.com/fusesoc/fusesoc.github.io) Integration
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