117 lines
3.9 KiB
Python
117 lines
3.9 KiB
Python
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from time import sleep
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from amaranth import *
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from amaranth.lib import io
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from manta import *
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class EthernetIOCoreExample(Elaboratable):
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def __init__(self, platform, port):
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self.platform = platform
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# Create Manta instance
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self.manta = Manta()
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# Configure it to communicate over Ethernet
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self.manta.interface = EthernetInterface(
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phy="LiteEthPHYRMII",
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device="xc7a",
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vendor="xilinx",
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toolchain="vivado",
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refclk_freq=50e6,
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clk_freq = 50e6,
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fpga_ip_addr = "10.0.0.2",
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host_ip_addr = "10.0.0.1",
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udp_port=2000,
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)
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# Autodetect the number of LEDs on the platform
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resources = platform.resources.keys()
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self.n_leds = max([i for name, i in resources if name == "led"])
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# Add IOCore to Manta instance
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self.leds = Signal(self.n_leds)
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self.manta.cores.io = IOCore(outputs=[self.leds])
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def elaborate(self, platform):
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m = Module()
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# Create 50MHz clock domain
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m.domains.ethclk = ethclk = ClockDomain()
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m.submodules.divider = Instance(
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"divider",
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("i", "clk", ClockSignal()),
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("o", "ethclk", ethclk.clk),
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)
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platform.add_file("divider.sv", open("divider.sv"))
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# Add Manta as a submodule
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m.submodules.manta = DomainRenamer("ethclk")(self.manta)
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# Wire each LED to Manta's IO Core output
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for i in range(self.n_leds):
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led = io.Buffer("o", platform.request("led", i, dir="-"))
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m.d.comb += led.o.eq(self.leds[i])
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m.submodules += led
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# Wire Ethernet pins to the Manta instance
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# This is only required for Amaranth < 0.5.2
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eth_pin_names = ["mdio", "mdc", "reset", "rxd", "rxerr", "txd", "txen", "crs_dv", "int", "clk"]
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eth_pin_dirs = {name: "-" for name in eth_pin_names}
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eth_pins = platform.request("eth", dir=eth_pin_dirs)
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# For Amaranth > 0.5.2, this simpler syntax may be used:
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# eth_pins = platform.request("eth")
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# self.manta.interface.set_phy_io(
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# rmii_clocks_ref_clk = eth_pins.clk,
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# rmii_rst_n = eth_pins.reset,
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# rmii_rx_data = eth_pins.rxd,
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# rmii_crs_dv = eth_pins.crs_dv,
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# rmii_tx_en = eth_pins.txen,
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# rmii_tx_data = eth_pins.txd,
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# rmii_mdc = eth_pins.mdc,
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# rmii_mdio = eth_pins.mdio,
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# )
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m.submodules.eth_clk_io_buf = eth_clk_io_buf = io.Buffer("o", eth_pins.clk)
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m.d.comb += eth_clk_io_buf.o.eq(ethclk.clk)
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self.manta.interface._phy_io = [
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("i", "rmii_clocks_ref_clk", ethclk.clk),
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("o", "rmii_rst_n", eth_pins.reset.io),
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("i", "rmii_rx_data", eth_pins.rxd.io),
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("i", "rmii_crs_dv", eth_pins.crs_dv.io),
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("o", "rmii_tx_en", eth_pins.txen.io),
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("o", "rmii_tx_data", eth_pins.txd.io),
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("o", "rmii_mdc", eth_pins.mdc.io),
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("io", "rmii_mdio", eth_pins.mdio.io),
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]
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return m
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def test(self):
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# Build and program the FPGA
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# self.platform.build(self, do_program=True)
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# Iterate through all the LEDs, blinking them off and on
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i = 0
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while True:
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self.manta.cores.io.set_probe("leds", 1 << i)
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i = (i + 1) % self.n_leds
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sleep(0.1)
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# Amaranth has a built-in build system, and well as a set of platform
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# definitions for a huge number of FPGA boards. The class defined above is
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# very generic, as it specifies a design independent of any particular FGPA
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# board. This means that by changing which platform you pass UARTIOCoreExample
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# below, you can port this example to any FPGA board!
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if __name__ == "__main__":
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from amaranth_boards.nexys4ddr import Nexys4DDRPlatform
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EthernetIOCoreExample(platform=Nexys4DDRPlatform(), port="auto").test()
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