37 lines
1.2 KiB
Tcl
37 lines
1.2 KiB
Tcl
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#!/usr/bin/tclsh
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set partNum xc7a100tcsg324-1
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set outputDir build
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read_verilog -sv [ glob *.{sv,v,svh,vh} ]
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read_xdc top_level.xdc
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set_part $partNum
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# synth
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synth_design -top top_level -part $partNum -verbose
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report_utilization -file $outputDir/post_synth_util.rpt
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report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
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report_timing -file $outputDir/post_synth_timing.rpt
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# place
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opt_design
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place_design
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phys_opt_design
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report_utilization -file $outputDir/post_place_util.rpt
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report_clock_utilization -file $outputDir/clock_util.rpt
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report_timing_summary -file $outputDir/post_place_timing_summary.rpt
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report_timing -file $outputDir/post_place_timing.rpt
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# route design and generate bitstream
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route_design -directive Explore
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write_bitstream -force $outputDir/out.bit
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report_route_status -file $outputDir/post_route_status.rpt
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report_timing_summary -file $outputDir/post_route_timing_summary.rpt
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report_timing -file $outputDir/post_route_timing.rpt
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report_power -file $outputDir/post_route_power.rpt
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report_drc -file $outputDir/post_imp_drc.rpt
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write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true
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